Abstract: A semiconductor device includes a first power rail, a second power rail, at least one standard cell and at least one power bridge. The first power rail extends in a first direction over a substrate. The second power rail extends in the first direction over the substrate, and the second power rail is spaced apart from the first power rail in a second direction that intersects the first direction. The at least one standard cell receives a first voltage from the first and the second power rails. The at least one power bridge connects the first power rail and the second power rail in the second direction. The first power rail and the second power rail are formed in a first metal layer and the least one power bridge is formed in a bottom metal layer that is under the first metal layer.

Abstract: A semiconductor device includes: first through fourth active regions spaced apart from one another; a first gate line disposed to overlap with the first and second active regions, but not with the third and fourth active regions, and to extend in a first direction; a second gate line disposed to overlap with the third and fourth active regions, but not with the first and second active regions, and to extend in the first direction while being spaced apart from the first gate line; and a dummy gate line disposed to overlap with the first through fourth active regions and a field region, to be spaced apart from the first and second gate lines in a second direction, and to extend in the first direction, wherein a signal input to the first or second active region is transmitted to the third or fourth active region.

Abstract: A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.

Abstract: An integrated circuit includes a plurality of positive edge-triggered master-slave flip-flop circuits sharing a clock signal. At least one of the positive edge-triggered master-slave flip-flop circuits includes; an input stage that provides a first output signal generated from an input signal in response to the clock signal and an inverted clock signal, a first inverting circuit that generates the inverted clock signal by delaying the clock signal, a transmission gate that receives a second output signal and generates a final output signal, and a second inverting circuit that receives the first output signal and generates the second output signal from the first output signal. The clock signal is applied to an NMOS transistor of the transmission gate and a PMOS transistor of the input stage, and the inverted clock signal is applied to a PMOS transistor of the transmission gate and an NMOS transistor of the input stage.

Abstract: Provided are a reusable polymeric material for removing siloxane compounds in biogas, a method for removing siloxane using the same, and an apparatus therefor, and more particularly, a polyacrylate-based polymer absorbent for removing siloxane compounds in biogas and a method for removing siloxane compounds in biogas. The method for removing siloxane compounds in biogas includes (a) providing the biogas, and b) absorbing the siloxane compounds in a polymer absorbent by passing the biogas through the polymer absorbent according to any one of claims 1 to 5.

Abstract: A semiconductor device may include a master latch that stores an input data signal, using a local power supply voltage and a clock signal, and outputs the input data signal to a first output signal; a slave latch that stores the first output signal, using a global power supply voltage, the clock signal and a retention signal, and outputs a second output signal; a first logic gate that receives input of one signal and another signal of the retention signal, the clock signal and the reset signal, and outputs a first control signal generated by performing a first logical operation; and a second logic gate that receives input of the rest of the retention signal, the clock signal and the reset signal, and the first control signal, and performs a second logical operation to at least one of the master latch and the slave latch.

Abstract: Provided is a semiconductor device including low power retention flip-flop. The semiconductor device includes a first line to which a global power supply voltage is applied, a second line to which a local power supply voltage is applied, the second line being separated from the first line, a first operating circuit connected to the second line to use the local power supply voltage, a first power gating circuit determining whether the local power supply voltage is applied to the first operating circuit and a first retention flip-flop connected to the first line and the second line, wherein the first retention flip-flop comprises a first circuit including a master latch, a second circuit including a slave latch, and a first tri-state inverter connected between the master latch and the slave latch.

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level.

Abstract: Disclosed herein is a secondary battery constructed in a structure in which an electrode assembly having a cathode/separator/anode arrangement is mounted in a battery case made of a laminate sheet including a resin layer and a metal layer, electrode tabs of the electrode assembly are coupled to corresponding electrode leads, and the electrode assembly is sealed in the battery case while electrode leads are exposed to the outside of the battery case, wherein a protective film is attached to coupling regions between the electrode tabs and the electrode leads for sealing the coupling regions between the electrode tabs and the electrode leads. The secondary battery according to the present invention is constructed in a structure in which the coupling regions are sealed by the protective film, unlike a conventional secondary battery constructed in a structure in which the coupling regions between the electrode tabs and the electrode leads are exposed in the battery case.

Abstract: A semiconductor device may include a first node coupled to a first pad to which a first voltage having a first voltage level is inputted; a second node coupled to a second pad to which a second voltage having a second voltage level is inputted; an internal voltage generation unit suitable for shifting a voltage level of the first node to generate an internal voltage having the second voltage level, and outputting the internal voltage to third and fourth nodes; a first internal circuit suitable for operating by employing a voltage of the second node; and a node coupling unit that electrically couples the second node to the third node during a test operation, and electrically separates the second node and the third node during a normal operation.

Abstract: Disclosed is an apparatus for decomposing low-concentration volatile organic compounds, which includes: an adsorption unit configured to adsorb a volatile organic compound; a heated air supply unit configured to supply a heated air to the adsorption unit; an oxidation decomposing catalyst unit configured to decompose a volatile organic compound detached from the adsorption unit; and an ozone supply unit configured to supply an ozone to the oxidation decomposing catalyst unit. The apparatus may maximize an exchange cycle semi-permanently by adsorbing low-concentration VOC under a high-flow condition and then detaching VOC within a short time and also by recycling an adsorption filter. In addition, the apparatus may effectively decompose VOC substances detached by a low flow into carbon dioxide and water under a condition with most excellent oxidation decomposition efficiency by using an oxidation decomposing catalyst filter.

Abstract: Disclosed is a technology related to an optical waveguide which is insensitive to an ambient temperature and is capable of adjusting a wavelength error due to a manufacturing processing deviation. The optical waveguide includes: a clad layer positioned on a substrate; a core layer positioned between the substrate and the clad layer, and including patterns positioned in a first region and a second region; and a wavelength adjusting unit positioned in the first region between the substrate and the clad layer, and configured to adjust a wavelength of an optical signal propagated through patterns passing through the first region based on received electric energy, in which the clad layer includes a material having a Thermo-Optic Coefficient (TOC) with an opposite sign to that of a material included in the core layer.

Abstract: An address generation device of a memory system includes an address generator and a synchronizer. The address generator may receive a clock and sequentially generate a first address and a second address after the first address. The synchronizer may synchronize the first address in response to the clock at a preset time point before the second address is generated by the address generator, and output the synchronized address as an output address.

Abstract: An integrated circuit includes a plurality of positive edge-triggered master-slave flip-flop circuits sharing a clock signal. At least one of the positive edge-triggered master-slave flip-flop circuits includes; an input stage that provides a first output signal generated from an input signal in response to the clock signal and an inverted clock signal, a first inverting circuit that generates the inverted clock signal by delaying the clock signal, a transmission gate that receives a second output signal and generates a final output signal, and a second inverting circuit that receives the first output signal and generates the second output signal from the first output signal. The clock signal is applied to an NMOS transistor of the transmission gate and a PMOS transistor of the input stage, and the inverted clock signal is applied to a PMOS transistor of the transmission gate and an NMOS transistor of the input stage.

Abstract: Provided is an apparatus for sealing an arc-tube including a jig body including an electrode pin hole into which an end part of the electrode pin inserted into a bypass tube part of the arc-tube is inserted and a connection path connected with the electrode pin hole; and a pressurizing means inserted into the connection path to pressurize and fix the electrode pin positioned at the electrode pin hole. Therefore, the apparatus for sealing an arc-tube can more easily and stably fix the electrode pin during a sealing process.

Abstract: A liquid crystal display device includes: a substrate; a thin film transistor disposed on the substrate; a pixel electrode connected with the thin film transistor; and a roof layer disposed to face the pixel electrode, wherein a plurality of microcavities having respective liquid crystal injection holes are formed between the pixel electrode and the roof layer, and the microcavities are filled with electrically orientatable liquid crystal molecules, wherein a light blocking layer disposed adjacent to the injection holes is formed and covering the thin film transistor, wherein the light blocking layer is covered by a passivation layer.

Abstract: The present invention provides a novel psicose epimerase derived from Flavonifractor plautii and capable of converting fructose to psicose. The novel psicose epimerase according to the present invention possesses an activity producing psicose by epimerizing the carbon-3 position of fructose, and has maximal activity for the conversion of fructose to psicose at a relatively high temperature and a pH less than or equal to neutral, has excellent thermal stability, and can mass-produce psicose from fructose in a high yield for a short amount of time. Therefore, the psicose epimerase according to the present invention is advantageous in the industrial production of psicose, and it is expected that the psicose produced thereby can be usefully utilized in the functional sugar industry and also as materials for health food, medicine, cosmetics, and the like using the psicose.

Abstract: A liquid crystal display includes: a first substrate on which a display area and a non-display area disposed on an outside of the display area are defined; a first insulating layer, which is disposed in the non-display area on the first substrate; a barrier pattern, which is disposed on the first insulating layer; a seal pattern, which is disposed on the barrier pattern to overlap the barrier pattern; and a second substrate, which is disposed to face the first substrate.

Abstract: A semiconductor memory device includes a first memory bank and a second memory bank; an address counter unit including: a first address counter suitable for outputting a first counting address signal corresponding to the first memory bank; and a second address counter suitable for outputting a second counting address signal corresponding to the second memory bank; a first output control unit suitable for generating first column address signals in response to the first counting address signal during a data input operation, and generating the first column address signals in response to the second counting address signal during a data output operation; and a second output control unit generating second column address signals in response to the second counting address signal during the data input operation and the data output operation.

Abstract: A voltage generator that includes an operation mode determination circuit suitable for determining an active mode or a standby mode based on a chip enable signal to activate an active mode signal or a standby mode signal according to a result of the determination; and a bulk voltage generation circuit outputting a bulk voltage having an internal power voltage when the active mode signal is activated, and outputting the bulk voltage having an external power voltage when the standby mode signal is activated.