Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level.

Abstract: Disclosed herein is a secondary battery constructed in a structure in which an electrode assembly having a cathode/separator/anode arrangement is mounted in a battery case made of a laminate sheet including a resin layer and a metal layer, electrode tabs of the electrode assembly are coupled to corresponding electrode leads, and the electrode assembly is sealed in the battery case while electrode leads are exposed to the outside of the battery case, wherein a protective film is attached to coupling regions between the electrode tabs and the electrode leads for sealing the coupling regions between the electrode tabs and the electrode leads. The secondary battery according to the present invention is constructed in a structure in which the coupling regions are sealed by the protective film, unlike a conventional secondary battery constructed in a structure in which the coupling regions between the electrode tabs and the electrode leads are exposed in the battery case.

Abstract: A semiconductor device may include a first node coupled to a first pad to which a first voltage having a first voltage level is inputted; a second node coupled to a second pad to which a second voltage having a second voltage level is inputted; an internal voltage generation unit suitable for shifting a voltage level of the first node to generate an internal voltage having the second voltage level, and outputting the internal voltage to third and fourth nodes; a first internal circuit suitable for operating by employing a voltage of the second node; and a node coupling unit that electrically couples the second node to the third node during a test operation, and electrically separates the second node and the third node during a normal operation.

Abstract: Disclosed is an apparatus for decomposing low-concentration volatile organic compounds, which includes: an adsorption unit configured to adsorb a volatile organic compound; a heated air supply unit configured to supply a heated air to the adsorption unit; an oxidation decomposing catalyst unit configured to decompose a volatile organic compound detached from the adsorption unit; and an ozone supply unit configured to supply an ozone to the oxidation decomposing catalyst unit. The apparatus may maximize an exchange cycle semi-permanently by adsorbing low-concentration VOC under a high-flow condition and then detaching VOC within a short time and also by recycling an adsorption filter. In addition, the apparatus may effectively decompose VOC substances detached by a low flow into carbon dioxide and water under a condition with most excellent oxidation decomposition efficiency by using an oxidation decomposing catalyst filter.

Abstract: Disclosed is a technology related to an optical waveguide which is insensitive to an ambient temperature and is capable of adjusting a wavelength error due to a manufacturing processing deviation. The optical waveguide includes: a clad layer positioned on a substrate; a core layer positioned between the substrate and the clad layer, and including patterns positioned in a first region and a second region; and a wavelength adjusting unit positioned in the first region between the substrate and the clad layer, and configured to adjust a wavelength of an optical signal propagated through patterns passing through the first region based on received electric energy, in which the clad layer includes a material having a Thermo-Optic Coefficient (TOC) with an opposite sign to that of a material included in the core layer.

Abstract: An address generation device of a memory system includes an address generator and a synchronizer. The address generator may receive a clock and sequentially generate a first address and a second address after the first address. The synchronizer may synchronize the first address in response to the clock at a preset time point before the second address is generated by the address generator, and output the synchronized address as an output address.

Abstract: An integrated circuit includes a plurality of positive edge-triggered master-slave flip-flop circuits sharing a clock signal. At least one of the positive edge-triggered master-slave flip-flop circuits includes; an input stage that provides a first output signal generated from an input signal in response to the clock signal and an inverted clock signal, a first inverting circuit that generates the inverted clock signal by delaying the clock signal, a transmission gate that receives a second output signal and generates a final output signal, and a second inverting circuit that receives the first output signal and generates the second output signal from the first output signal. The clock signal is applied to an NMOS transistor of the transmission gate and a PMOS transistor of the input stage, and the inverted clock signal is applied to a PMOS transistor of the transmission gate and an NMOS transistor of the input stage.

Abstract: Provided is an apparatus for sealing an arc-tube including a jig body including an electrode pin hole into which an end part of the electrode pin inserted into a bypass tube part of the arc-tube is inserted and a connection path connected with the electrode pin hole; and a pressurizing means inserted into the connection path to pressurize and fix the electrode pin positioned at the electrode pin hole. Therefore, the apparatus for sealing an arc-tube can more easily and stably fix the electrode pin during a sealing process.

Abstract: A liquid crystal display device includes: a substrate; a thin film transistor disposed on the substrate; a pixel electrode connected with the thin film transistor; and a roof layer disposed to face the pixel electrode, wherein a plurality of microcavities having respective liquid crystal injection holes are formed between the pixel electrode and the roof layer, and the microcavities are filled with electrically orientatable liquid crystal molecules, wherein a light blocking layer disposed adjacent to the injection holes is formed and covering the thin film transistor, wherein the light blocking layer is covered by a passivation layer.

Abstract: The present invention provides a novel psicose epimerase derived from Flavonifractor plautii and capable of converting fructose to psicose. The novel psicose epimerase according to the present invention possesses an activity producing psicose by epimerizing the carbon-3 position of fructose, and has maximal activity for the conversion of fructose to psicose at a relatively high temperature and a pH less than or equal to neutral, has excellent thermal stability, and can mass-produce psicose from fructose in a high yield for a short amount of time. Therefore, the psicose epimerase according to the present invention is advantageous in the industrial production of psicose, and it is expected that the psicose produced thereby can be usefully utilized in the functional sugar industry and also as materials for health food, medicine, cosmetics, and the like using the psicose.

Abstract: A liquid crystal display includes: a first substrate on which a display area and a non-display area disposed on an outside of the display area are defined; a first insulating layer, which is disposed in the non-display area on the first substrate; a barrier pattern, which is disposed on the first insulating layer; a seal pattern, which is disposed on the barrier pattern to overlap the barrier pattern; and a second substrate, which is disposed to face the first substrate.

Abstract: A semiconductor memory device includes a first memory bank and a second memory bank; an address counter unit including: a first address counter suitable for outputting a first counting address signal corresponding to the first memory bank; and a second address counter suitable for outputting a second counting address signal corresponding to the second memory bank; a first output control unit suitable for generating first column address signals in response to the first counting address signal during a data input operation, and generating the first column address signals in response to the second counting address signal during a data output operation; and a second output control unit generating second column address signals in response to the second counting address signal during the data input operation and the data output operation.

Abstract: A voltage generator that includes an operation mode determination circuit suitable for determining an active mode or a standby mode based on a chip enable signal to activate an active mode signal or a standby mode signal according to a result of the determination; and a bulk voltage generation circuit outputting a bulk voltage having an internal power voltage when the active mode signal is activated, and outputting the bulk voltage having an external power voltage when the standby mode signal is activated.

Abstract: A semiconductor integrated circuit includes a scan enable (SE) inverter and a clock (CK) inverter on a substrate, a first multiplex part, and a second multiplex part. The SE inverter and the CK inverter are aligned in a first direction. The first multiplex part includes a first wiring and a first transistor, the first wiring is connected to a power supply voltage part of the SE inverter, and the first wiring and the first transistor share a source region contacting the first wiring. The second multiplex part includes a second wiring and a second transistor, the second wiring is connected to a power supply voltage part of the CK inverter, and the second wiring and the second transistor share a source region contacting the second wiring. The SE inverter and the CK inverter are aligned in a first direction to each other.

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit determines a logic level of a second node and a logic level of a third node, on the basis of a logic level of input data, a logic level of a clock signal, and a logic level of a first node. The second circuit determines the logic level of the first node, on the basis of the logic level of the clock signal, the logic level of the second node and the logic level of the third node. The first circuit comprises a sub-circuit and a first transistor. The first circuit determines the logic level of the second node, on the basis of the logic level of the input data and the logic level of the first node. The first transistor is gated to the logic level of the clock signal to connect the third node with the second node.

Abstract: An electronic device is provided. The electronic device includes a battery, a power management integrated circuit (PMIC), that is electrically connected to the battery, adjusts at least part of power received from the battery, and outputs a controlled power, a processor electrically connected to the PMIC, at least one power sensor that is one of electrically connected between the battery and the PMIC and constitutes a part of the PMIC, and a control circuit electrically connected to the at least one power sensor. The control circuit acquires at least one of a current value and a power value input into the PMIC from the battery, determines whether at least one of the acquired current value and power value is greater than or equal to a threshold, and generates a first signal for controlling at least one of the PMIC and the processor, at least partially based on the determination.

Abstract: A semiconductor memory device includes a first page buffer block and a second page buffer block corresponding to a first memory bank and a second memory bank, respectively, an input/output control circuit suitable for transferring input data to data lines, a first column decoder and a second column decoder suitable for latching the input data transferred through the data lines to the first page buffer block and the second page buffer block, respectively, based on a column address transferred through address lines that are shared by the first and second column decoders, and a control signal generation circuit suitable for generating a plurality of page buffer selection signals to control the first and second column decoders to selectively perform data latch operations on the first and second page buffer blocks.

Abstract: An electronic device includes: a communication interface configured to support a communication function; and one or more processors configured to perform a temperature detection of the electronic device during the communication function execution, drive a timer warning a communication function termination if the detected temperature information satisfies a specified temperature condition, and output count information corresponding to the timer driving.

Abstract: A superluminescent diode and a method for implementing the same, wherein the method includes growing a first epi layer on top of an SI (semi-insulating substrate); re-growing a butt based on the first epi layer; forming a tapered SSC (spot size converter) on the re-grown butt layer; forming an optical waveguide on an active area that is based on the first epi layer and on an SSC area that is based on the tapered SSC; forming an RWG on the optical waveguide; and forming a p-type electrode and an n-type electrode.

Abstract: Disclosed is a catalyst filter, which includes a catalyst support and a nano metallic catalyst sprayed to a surface of the catalyst support. The catalyst filter uses catalyst slurry prepared by using a particulate catalyst, in which a small amount of nano metallic catalyst exhibiting a catalyst performance is sprayed to a surface of the catalyst support, different from an existing patent technique in which catalyst particles are formed and prepared as a support to consume a large amount of catalyst. Therefore, the specific surface area of the catalyst filter is not smaller than the specific surface area of the nano catalyst particles, and thus the catalyst filter may effectively remove and decompose ultra-low concentration gas-state contaminants in an indoor air.