Patents by Inventor Min Yuan

Min Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7279329
    Abstract: A DNA molecule consisting of the nucleotide sequence of SEQ ID NO: 1, which encodes a collagenous (COL1) domain and a C-terminal noncollagenous (NC1) domain of type XXI collagen. Expression systems and methods for the expression of the DNA molecule are also provided.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: October 9, 2007
    Assignee: Industrial Technology Research Institute
    Inventors: Min-Yuan Chou, Hsiu-Chuan Li, Chuan-Chuan Huang
  • Patent number: 7277315
    Abstract: Methods and circuits to reduce power consumption of DRAM local word-line drivers are disclosed. A first voltage converter provides a voltage VPP1, which is lower than the voltage VPP required to operate a word-line of a DRAM cell array. A voltage detector monitors the voltage level of the local word-line driver. Once the voltage level VPP1 is reached on the local word-linedriver switching means as e.g. tri-state drivers put the final VPP voltage on the word line. This VPP voltage is the output of a second voltage boost converter. Putting the voltage in two stages on the word-line reduces the overall power consumption. The voltage level VPP1 has to be carefully selected to find a compromised solution between current consumption and performance.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: October 2, 2007
    Assignee: Etron Technology, Inc.
    Inventors: Der-Min Yuan, Jen Shou Hsu, Yao Yi Liu
  • Patent number: 7271048
    Abstract: A method of manufacturing a trench MOSFET with high cell density is disclosed. The method introduces a sidewall oxide spacer for narrowing the opening of the trench structure, thereby decreasing the cell pitch of the memory units. Moreover, the source structure is formed automatically by means of an extra contact silicon etch for preventing the photoresist from lifting during the ion implantation of the prior art. On the other hand, the contact structure is filled with W-plug for overcoming the defect of poor metal step coverage resulted from filling the contact structure with AlSiCu according to the prior art. Thus, the cell density of the device can be increased; and the Rds-on and the power loss of the device can be decreased.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: September 18, 2007
    Assignee: Mosel Vitelic, Inc.
    Inventors: Chien-Ping Chang, Mao Song Tseng, Hsin Huang Hsieh, Tien-Min Yuan
  • Patent number: 7262067
    Abstract: A method for monitoring copper film quality and for evaluating the annealing efficiency of a copper annealing process includes measuring hardness of a copper film formed on a substrate before and after annealing and comparing the hardness measurement results. The measurements can be correlated to grain boundary saturation levels, copper grain sizes and therefore conductivity. Hardness measurements may be taken at a plurality of locations throughout the substrate to account for variations in the copper film grain structure.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: August 28, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hsien-Ping Feng, Min-Yuan Cheng, Hsi-Kuei Cheng, Steven Lin, Huang-Yi Huang, Yuh-Da Fan
  • Patent number: 7256120
    Abstract: A method of forming a metal layer with reduced defects comprising providing a structure having a dielectric layer formed over it, forming a dielectric layer having an opening, lining the opening with a metal seed layer, treating the metal seed layer with a cleaning process to remove contaminates from it, and forming a metal layer upon the metal seed layer.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: August 14, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co.
    Inventors: Jung-Chin Tsao, Chi-Wen Liu, Hsien-Ping Feng, Hsi-Kuei Cheng, Steven Lin, Min-Yuan Cheng
  • Publication number: 20070153600
    Abstract: Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and precharging is kept to a minimum. A test DRAM cell is used to determine the exact time required for data sensing. Furthermore no precharging is performed during WRITE-operations. In case data is changing from “1” to “0” or vice versa data lines are inverted accordingly during WRITE operation.
    Type: Application
    Filed: January 4, 2006
    Publication date: July 5, 2007
    Inventors: Der-Min Yuan, Shih-Hsing Wang
  • Publication number: 20070143649
    Abstract: A test method and implementation is described to test an internal data path within a DDR DRAM during a read operation. A worse case test sequence and a compliment of the worse case test sequence is stored within memory. The test sequence and its compliment are arranged within a data word such that upon read out of the data word, the test sequences or the compliment of the test sequences is applied to a plurality of wire connections of the internal data path. Each test sequence comprises a plurality of logical bits of the same value followed by a bit of the opposite value, which tests for charge buildup on each element of the internal data path. Adjacent elements of the internal data path connect test sequences that are compliments to maximize voltage differentials and enhance possibility of signal coupling between wire elements of the internal data path.
    Type: Application
    Filed: December 21, 2005
    Publication date: June 21, 2007
    Inventor: Der-Min Yuan
  • Publication number: 20070133317
    Abstract: Methods and circuits to reduce power consumption of DRAM local word-line drivers are disclosed. A first voltage converter provides a voltage VPP1, which is lower than the voltage VPP required to operate a word-line of a DRAM cell array. A voltage detector monitors the voltage level of the local word-line driver. Once the voltage level VPP1 is reached on the local word-linedriver switching means as e.g. tri-state drivers put the final VPP voltage on the word line. This VPP voltage is the output of a second voltage boost converter. Putting the voltage in two stages on the word-line reduces the overall power consumption. The voltage level VPP1 has to be carefully selected to find a compromised solution between current consumption and performance.
    Type: Application
    Filed: December 14, 2005
    Publication date: June 14, 2007
    Inventors: Der-Min Yuan, Jen Hsu, Yao Liu
  • Publication number: 20070087405
    Abstract: A DNA molecule consisting of the nucleotide sequence of SEQ ID NO: 1, which encodes a collagenous (COL1) domain and a C-terminal noncollagenous (NC1) domain of type XXI collagen. Expression systems and methods for the expression of the DNA molecule are also provided.
    Type: Application
    Filed: October 17, 2005
    Publication date: April 19, 2007
    Inventors: Min-Yuan Chou, Hsiu-Chuan Li, Chuan-Chuan Huang
  • Patent number: 7205196
    Abstract: The present invention provides a manufacturing process and the structure of an integrated circuit. In one embodiment, one polysilicon layer deposition and one polysilicon layer etching are used to form the gate of a trench device and the polysilicon layer of a planar device simultaneously. The present invention not only has overcome the problem of the electric leakage, but also has the advantages of withstanding a higher voltage, reducing the relevant cost and increasing the yields. The present invention possesses the outstanding technical features in the field of the power device.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: April 17, 2007
    Assignee: Mosel Vitelic, Inc.
    Inventors: Hsin-Huang Hsieh, Chien-Ping Chang, Mao-Song Tseng, Tien-Min Yuan
  • Patent number: 7184341
    Abstract: A new method of increasing access cycle time in a memory device is achieved. The memory device has three operating states of standby, read, and write. The data lines in the memory device may be pre-charged. The method comprises, first, during the standby state, the data lines are pre-charge. Second, during the write state, the data lines are not pre-charged. Third, during the read state, the data lines are not pre-charged. During a transition from the write state to the read state, the data lines are pre-charged.
    Type: Grant
    Filed: July 26, 2004
    Date of Patent: February 27, 2007
    Assignee: Etron Technology, Inc.
    Inventors: Der-Min Yuan, Chiun-Chi Shen
  • Patent number: 7179099
    Abstract: The mean for the universal serial bus hide and swing, its body inside have a sliding unit its head pivot to establish on can swing from as of deal with USB, and a memory to equip the electricity conjunction in deal with USB. The USB can conceal in the body, or along with the sliding unit to swing after being moved the indentation of the body.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: February 20, 2007
    Assignee: Tul Cooperation
    Inventor: Min Yuan Hsieh
  • Publication number: 20070006405
    Abstract: A wafer cleaning system is provided. The wafer cleaning system comprises a first brush, a second brush, a brush motor, and a controller. The second brush is positioned parallel to the first brush. The brush motor moves at least one of the first and second brushes from a first position to a second position according to a driving current of the brush motor.
    Type: Application
    Filed: July 7, 2005
    Publication date: January 11, 2007
    Inventors: Hsien-Ping Feng, Min-Yuan Cheng, Jia-Jia Lin, Chieh-Tsao Wang, Shu-Wen Fu, Steven Lin, Ray Chuang
  • Publication number: 20060196765
    Abstract: A method for forming a microelectronic layer while employing a sputtering method employs a reactor chamber. A sputtering target and a substrate are positioned within the reactor chamber, along with a sputtering target heater at a side of sputtering target opposite the substrate. At least one of: (1) a heater to sputtering target distance; (2) sputtering power; (3) deposition time; and (4) sputtering gas flow rate, is controlled in accord with a pre-determined function of sputtering target lifetime to provide enhanced uniformity of the deposited layer.
    Type: Application
    Filed: March 7, 2005
    Publication date: September 7, 2006
    Inventors: Hsi-Kuei Cheng, Chieh-Tsao Wang, Hsien-Ping Feng, Min-Yuan Cheng, Jung-Chin Tsao, Steven Lin, Ray Chuang, Chyi-Tsong NI
  • Publication number: 20060141768
    Abstract: A method of forming a metal layer with reduced defects comprising providing a structure having a dielectric layer formed over it, forming a dielectric layer having an opening, lining the opening with a metal seed layer, treating the metal seed layer with a cleaning process to remove contaminates from it, and forming a metal layer upon the metal seed layer.
    Type: Application
    Filed: December 28, 2004
    Publication date: June 29, 2006
    Inventors: Jung-Chin Tsao, Chi-Wen Liu, Hsien-Ping Feng, Hsi-Kuei Cheng, Steven Lin, Min-Yuan Cheng
  • Publication number: 20060136861
    Abstract: A method for improving manufacturability of a design includes performing space or enclosure checks on multiple interacting layers of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design database to decrease the risk of features widths, feature spaces or feature enclosures being patterned smaller than designed. In some embodiments, the upsized features are larger in the wafer circuit pattern than are drawn in a designed database. The method for improving manufacturability of a design, in some embodiments, is stored on a computer readable storage medium.
    Type: Application
    Filed: December 21, 2004
    Publication date: June 22, 2006
    Inventors: Kevin Lucas, Robert Boone, Mehul Shroff, Kirk Strozewski, Chi-Min Yuan, Jason Porter
  • Publication number: 20060098417
    Abstract: A shielding structure for a control module installed on the surface of a rear cover of a display comprises a plurality of engaging portions disposed at both lateral sides of the control module installed on the rear cover of the display, a shielding cover in which the control module can be accepted and a plurality of engaging sheets extended from the lateral sides of the shielding cover. When the shielding cover is assembled on the rear cover, the shielding cover can be quickly fixed on or detached from the surface of the rear cover of the display through the matching engagement of the clipping portions on the rear cover and the engaging sheets.
    Type: Application
    Filed: August 11, 2005
    Publication date: May 11, 2006
    Inventors: Min Yuan, Chien Chueh
  • Publication number: 20060064247
    Abstract: Provided herein is a method and computer program product for designing and/or simulating a biotechnology experiment in silico; and for providing and generating revenue from a customized list of one or more biotechnology products and/or services related to the in silico designed or simulated biotechnology experiment or the product of that experiment. In illustrative examples, the products and or services are indirectly related to a biomolecule designed by the in silico designed biotechnology experiment. In addition, provided herein is a method and computer system for generating revenue, that includes providing a customer with a first computer program product for designing or performing a biotechnology experiment in silico; and providing the customer with access to a purchase function for purchasing a second computer program product for designing or performing a biotechnology experiment in silico.
    Type: Application
    Filed: July 14, 2005
    Publication date: March 23, 2006
    Inventors: Shao-Min Yuan, Michael Beltsov, Thomas Chappell, Kevin Clancy, Peter McGarvey, Sam Zaremba, James Caffrey, Konstantin Belov, Anatoliy Mnev, Siamak Baharloo, Aruna Myneni, James Gilmore
  • Publication number: 20060060728
    Abstract: A panel structure capable of being attached with or detached from a supporting stand mainly comprises a base seat installed at a panel, a base plate installed at the upper end of the supporting stand and a sliding mass capable of being slid in the base seat. Whereby, the base plate in an accepting groove of the base seat can directly be pressed and positioned in the accepting groove through the sliding mass so that the panel can be chosen to be assembled with or detached from the supporting stand depending on the place and the requirement if is practically used.
    Type: Application
    Filed: December 22, 2004
    Publication date: March 23, 2006
    Inventor: Min Yuan
  • Publication number: 20060046397
    Abstract: A method of manufacturing a trench MOSFET with high cell density is disclosed. The method introduces a sidewall oxide spacer for narrowing the opening of the trench structure, thereby decreasing the cell pitch of the memory units. Moreover, the source structure is formed automatically by means of an extra contact silicon etch for preventing the photoresist from lifting during the ion implantation of the prior art. On the other hand, the contact structure is filled with W-plug for overcoming the defect of poor metal step coverage resulted from filling the contact structure with AlSiCu according to the prior art. Thus, the cell density of the device can be increased; and the Rds-on and the power loss of the device can be decreased.
    Type: Application
    Filed: August 12, 2005
    Publication date: March 2, 2006
    Applicant: MOSEL VITELIC, INC.
    Inventors: Chien-Ping Chang, Mao Tseng, Hsin Hsieh, Tien-Min Yuan