Patents by Inventor Min Yuan

Min Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • IMMEDIATE RESPONSE LOW DROPOUT REGULATION SYSTEM AND OPERATION METHOD OF A LOW DROPOUT REGULATION SYSTEM
    Publication number: 20130234684
    Abstract: An immediate response low dropout regulation system includes a low dropout regulation unit, a tracking voltage generation unit, and a self-driving unit. The low dropout regulation unit is used for generating and outputting an inner output voltage according to a reference voltage. The tracking voltage generation unit is used for generating and outputting a tracking voltage according to the reference voltage. The self-driving unit is coupled to the low dropout regulation unit and the tracking voltage generation unit. When a voltage difference between the tracking voltage and the inner output voltage is greater than a constant times threshold voltage, the self-driving unit provides a compensation current to an output terminal of the low dropout regulation unit.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 12, 2013
    Applicant: Etron Technology, Inc.
    Inventors: Yen-An Chang, Kuang-Fu Teng, Der-Min Yuan
  • ELECTRONIC APPARATUS
    Publication number: 20130229313
    Abstract: An electronic apparatus includes a casing, a circuit board, and a feeding element. The casing is made of conducting material, and comprises at least one feeding point. The circuit board is disposed in the casing. The feeding element is disposed in the electronic apparatus, and contacts the feeding point of the casing for transmitting signals between the circuit board and the casing, so that the casing functions as a radiation body of an antenna. Accordingly, the signal shielding of the antenna can be avoided, and it is unnecessary to change the material of the casing to plastic, which needs additional manufacturing process. After several times of tests, configuring the feeding point at the corner of the casing can provide higher performance of transmission.
    Type: Application
    Filed: December 18, 2012
    Publication date: September 5, 2013
    Applicant: ASUSTEK COMPUTER INC.
    Inventor: Min-Yuan CHIU
  • ANTI-HUMAN EPIDERMAL GROWTH FACTOR RECEPTOR ANTIBODY AND USES THEREOF
    Publication number: 20130171174
    Abstract: An anti-human epidermal growth factor receptor (EGFR) antibody including an amino acid sequence as set forth in SEQ ID No. 3 is provided. The antibody binding to a labeling agent and used for labeling cells is also provided. A novel method for screening an anti-EGFR antibody is further provided.
    Type: Application
    Filed: September 12, 2012
    Publication date: July 4, 2013
    Inventors: Hsiang-Ching WANG, Ming-Hua Yang, Ling-Mei Wang, Min-Yuan Chou, Jyuan-Jyuan Syu
  • ANTI-HUMAN TRANSFERRIN RECEPTOR ANTIBODY AND USES THEREOF
    Publication number: 20130171061
    Abstract: One embodiment of the disclosure provides an amino sequence of an anti-human transferrin receptor antibody, including: an amino sequence of a heavy chain variable region which is represented by SEQ ID NO.: 1 or SEQ ID NO.: 2, wherein the anti-human transferrin receptor antibody is capable of specifically binding to a human transferrin receptor.
    Type: Application
    Filed: September 11, 2012
    Publication date: July 4, 2013
    Inventors: Ming-Hua YANG, Min-Yuan Chou, Hsiang-Ching Wang
  • Fc FUSION PROTEINS
    Publication number: 20130164286
    Abstract: The embodiments of the invention relate to compositions, methods, and kits comprising a fusion protein. The fusion proteins of the embodiments include monomer polypeptides which in one embodiment have at least a binding domain, an optional hinge region, a collagen-like domain and the Fc domain of a human IgG.
    Type: Application
    Filed: August 17, 2012
    Publication date: June 27, 2013
    Inventors: Min-Yuan CHOU, Wei-Chun Chiu, Ya-Ping Lai
  • Delay lock loop system with a self-tracking function and method thereof
    Patent number: 8432206
    Abstract: A delay lock loop system includes a timing controller, an OR gate, an input buffer, a pulse generator, and a delay lock loop. The timing controller is used for outputting an external enable signal periodically while a power saving signal is at a logic-low voltage, and being disabled according to a logic-high voltage of the power saving signal. The pulse generator is used for generating a pulse according to the positive edge of the power saving signal. The OR gate is coupled to the timing controller for receiving the power saving signal, the pulse, and the external enable signal, and outputting an enable signal according to the power saving signal and the external enable signal. The delay lock loop is coupled to the OR gate and the input buffer for enabling the delay lock loop again according to the enable signal.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: April 30, 2013
    Assignee: Etron Technology, Inc.
    Inventors: Der-Min Yuan, Kuang-Fu Teng, Chun Shiah, Feng-Chia Chang
  • MEMORY ACCESS CIRCUIT FOR DOUBLE DATA/SINGLE DATA RATE APPLICATIONS
    Publication number: 20130064018
    Abstract: A memory access circuit includes a write data circuit and a first write switch circuit. The write data circuit is used for receiving double data rate data or single data rate data, and outputting odd term data and even term data of adjusted double data rate data or adjusted single data rate data. The first write switch circuit is used for outputting the odd term data of the adjusted double data rate data to an odd block of a memory and outputting the even term data of the adjusted double data rate data to an even block of the memory when the write data circuit receives the double data rate data, and outputting the adjusted single data rate data to the even block or the odd block of the memory when the write data circuit receives the single data rate data.
    Type: Application
    Filed: June 28, 2012
    Publication date: March 14, 2013
    Inventors: Chih-Huei Hu, Chia-Wei Chang, Der-Min Yuan
  • HIGH SPEED BASEBOARD MANAGEMENT CONTROLLER AND TRANSMISSION METHOD THEREOF
    Publication number: 20130019030
    Abstract: A baseboard management controller is disclosed. The baseboard management controller adapted to monitor a host comprises a baseboard management control module, a memory controller and a video graphic array (VGA) module. The VGA module comprises a video controller, a decoder, a select circuit and a mapping circuit. The decoder receives a transaction signal from a first local bus and decodes a first address signal contained in the transaction signal. The select circuit selectively transfers data from one of the microprocessor bus, the video controller and the memory controller back to the first local bus according to a control signal. The mapping circuit being connected with the decoder maps the first address signal and a second address signal to a third address signal, updates the first address signal and transfers an updated transaction signal.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 17, 2013
    Inventors: Hung-Ju Huang, Shu-An Huang Ho, Jen-Min Yuan
  • Methods and Compositions for Nanoparticle-Mediated Cancer Cell-Targeted Delivery
    Publication number: 20130011333
    Abstract: The present invention provides methods and compositions to selectively and directly deliver nanoparticles carrying an active agent to tumor cells. The active agent is internalized by the tumor cells, producing an anti-tumor effect for therapeutic applications and/or depositing a detectable marker for diagnostic applications. The present invention further provides a p53 chimera that circumvents the dominant negative activity of mutant p53 as a therapeutic in the treatment of cancer and reduction of mor size.
    Type: Application
    Filed: January 18, 2011
    Publication date: January 10, 2013
    Applicant: Board of Regents, The University of Texas System
    Inventors: Zhi-Min Yuan, Seog-Jin Seo
  • Memory having a disabling circuit and method for disabling the memory
    Patent number: 8345500
    Abstract: A memory with disabling circuit includes a memory matrix and a disabling circuit. The memory matrix includes a data input/output end and an output enable end. The disabling circuit includes a fuse and an output end. When the fuse is not blown, the disabling circuit transmits the signal of the data input/output end to the output end according to the signal of the output enable end. When the fuse is blown, the disabling circuit generates a tri-state to the output end. Therefore, external circuits cannot perform actions of reading or writing to access the memory matrix.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: January 1, 2013
    Assignee: Etron Technology, Inc.
    Inventors: Shih-Hsing Wang, Der-Min Yuan
  • USE OF ARSENIC FOR CANCER THERAPY PROTECTION
    Publication number: 20120294955
    Abstract: A method of inhibiting, preventing, or reducing damage to non-cancerous cells in a human subject during chemotherapeutic treatment or radiation treatment of cancer cells in the human subject includes administering to the human subject arsenic and/or one or more compounds of arsenic in a therapeutically effective amount prior to treatment with radiation or one or more chemotherapeutic agents.
    Type: Application
    Filed: May 18, 2011
    Publication date: November 22, 2012
    Inventor: Zhi-Min Yuan
  • DELAY LOCK LOOP SYSTEM WITH A SELF-TRACKING FUNCTION AND METHOD THEREOF
    Publication number: 20120256666
    Abstract: A delay lock loop system includes a timing controller, an OR gate, an input buffer, a pulse generator, and a delay lock loop. The timing controller is used for outputting an external enable signal periodically while a power saving signal is at a logic-low voltage, and being disabled according to a logic-high voltage of the power saving signal. The pulse generator is used for generating a pulse according to the positive edge of the power saving signal. The OR gate is coupled to the timing controller for receiving the power saving signal, the pulse, and the external enable signal, and outputting an enable signal according to the power saving signal and the external enable signal. The delay lock loop is coupled to the OR gate and the input buffer for enabling the delay lock loop again according to the enable signal.
    Type: Application
    Filed: March 20, 2012
    Publication date: October 11, 2012
    Inventors: Der-Min Yuan, Kuang-Fu Teng, Chun Shiah, Feng-Chia Chang
  • Voltage regulator for memory
    Patent number: 8284628
    Abstract: A voltage regulator includes a first transistor, a second transistor, a third transistor, a feedback unit, a comparison unit, a first control unit and a second control unit. The first transistor is controlled by the feedback unit and the comparison unit, for stabilizing the voltage of the output node. When the first control unit turns on the second transistor, the voltage of the output node rises. When the first control unit turns off the second transistor, it triggers the second control unit turning on the third transistor, so the first transistor is turned on completely. Therefore, when the third transistor is turned off, the first transistor can be controlled by the feedback unit and the comparison unit for stabilizing the voltage of the output node.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: October 9, 2012
    Assignee: Etron Technology, Inc.
    Inventors: Chun-Ching Hsia, Yen-An Chang, Der-Min Yuan
  • ELECTRONIC DEVICE AND FAN CONTROL METHOD
    Publication number: 20120253490
    Abstract: An electronic device including an audio module, a monitoring module and a fan is provided. The audio module generates an audio signal and an audio parameter according to audio data, and transmits the audio signal to a play device. Furthermore, the monitoring module determines a speed of fan rotation base on the type of the play device, the audio parameter and a sensed temperature. Then, a rotation speed of the fan is adjusted according to the determined speed of fan rotation.
    Type: Application
    Filed: June 1, 2011
    Publication date: October 4, 2012
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Chien-Ming Su, Min-Yuan Lin, Hsiang-Tien Wu, Zuo-Yu Huang
  • METHODS AND SYSTEMS FOR IN SILICO EXPERIMENTAL DESIGN AND FOR PROVIDING A BIOTECHNOLOGY PRODUCT TO A CUSTOMER
    Publication number: 20120221432
    Abstract: Provided herein is a method and computer program product for designing and/or simulating a biotechnology experiment in silico; and for providing and generating revenue from a customized list of one or more biotechnology products and/or services related to the in silico designed or simulated biotechnology experiment or the product of that experiment. In illustrative examples, the products and or services are indirectly related to a biomolecule designed by the in silico designed biotechnology experiment. In addition, provided herein is a method and computer system for generating revenue, that includes providing a customer with a first computer program product for designing or performing a biotechnology experiment in silico; and providing the customer with access to a purchase function for purchasing a second computer program product for designing or performing a biotechnology experiment in silico.
    Type: Application
    Filed: June 1, 2010
    Publication date: August 30, 2012
    Applicant: LIFE TECHNOLOGIES CORPORATION
    Inventors: Shao-Min Yuan, Michael Beltsov, Thomas G. Chappell, Kevin Clancy, Peter McGarvey, Sam Zaremba, James Caffrey, Konstantin Belov, Anatoliy Mnev, Siamak BAHARLOO, Aruna Myneni, James Gilmore
  • Method of reducing current of memory in self-refreshing mode and related memory
    Patent number: 8228751
    Abstract: The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a word line, and a second terminal. The method includes: after the memory enters the self-refreshing mode: controlling a voltage difference between the control terminal and the second terminal to correspond to a first value during a self-refreshing operation period; and controlling a voltage difference between the control terminal and the second terminal to correspond to a second value smaller than the first value during a non self-refreshing operation period.
    Type: Grant
    Filed: October 10, 2010
    Date of Patent: July 24, 2012
    Assignee: Etron Technology, Inc.
    Inventor: Der-Min Yuan
  • Chip testing circuit
    Patent number: 8169228
    Abstract: A chip testing circuit is disclosed. The chip testing circuit uses a judging circuit to switch the connection of the data compressing circuit between data compressing base units which compresses 4 XIOs, so as to obtain testing data by one single interface circuit and to increase the testing throughput.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: May 1, 2012
    Assignee: Etron Technology, Inc.
    Inventors: Der-Min Yuan, Yi-Hao Chang, Peng-Yu Chen
  • HUMANIZED ANTI-HUMAN TUMOR NECROSIS FACTOR ALPHA MONOCLONAL ANTIBODY AND SEQUENCE THEREOF
    Publication number: 20120100132
    Abstract: An amino acid sequence of a humanized monoclonal antibody includes an amino acid sequence of a light chain variable region, which includes SEQ ID. NO.: 1; and an amino acid sequence of a heavy chain variable region, which comprises SEQ ID. NO.: 2, wherein SEQ ID. NO.: 1 and SEQ ID. NO.: 2 have at least one amino acid substitution which is selected from a group consisting of isoleucine at position 10 of SEQ ID. NO.: 1, being substituted with threonine, lysine at position 18 of SEQ ID. NO.: 1, being substituted with arginine, lysine at position 2 of SEQ ID. NO.: 2, being substituted with glutamine, tryptophan at position 10 of SEQ ID. NO.: 2, being substituted with leucine, lysine at position 18 of SEQ ID. NO.: 2, being substituted with arginine and glutamic acid at position 41 of SEQ ID. NO.: 2, being substituted with glycine.
    Type: Application
    Filed: December 27, 2010
    Publication date: April 26, 2012
    Inventors: Wei-Chun CHIU, Min-Yuan Chou
  • Method of reducing current of memory in self-refreshing mode and related memory
    Patent number: 8154940
    Abstract: The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a word line, and a second terminal. The method includes: after the memory enters the self-refreshing mode: controlling a voltage difference between the control terminal and the second terminal to correspond to a first value during a self-refreshing operation period; and controlling a voltage difference between the control terminal and the second terminal to correspond to a second value smaller than the first value during a non self-refreshing operation period.
    Type: Grant
    Filed: October 10, 2010
    Date of Patent: April 10, 2012
    Assignee: Etron Technology, Inc.
    Inventor: Der-Min Yuan
  • Flat panel display
    Patent number: D674806
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: January 22, 2013
    Assignee: Compal Electronics Inc.
    Inventors: Min-Yuan Lin, Chang-Yuan Wu, Chien-Ming Su, Hsiang-Tien Wu, Yao-Kuang Su