Abstract: A method of inhibiting damage to non-cancerous cells in a human subject during chemotherapeutic treatment or radiation treatment of cancer cells in the human subject includes administering to the human subject arsenic and/or one or more compounds of arsenic in a therapeutically effective amount prior to treatment with radiation or one or more chemotherapeutic agents.

Abstract: A memory with disabling circuit includes a memory matrix and a disabling circuit. The memory matrix includes a data input/output end and an output enable end. The disabling circuit includes a fuse and an output end. When the fuse is not blown, the disabling circuit transmits the signal of the data input/output end to the output end according to the signal of the output enable end. When the fuse is blown, the disabling circuit generates a tri-state to the output end. Therefore, external circuits cannot perform actions of reading or writing to access the memory matrix.

Abstract: A data detecting apparatus and a data detecting method are disclosed in the embodiments of the present invention. The data detecting apparatus operates according to a clock signal with a predetermined period. The data detecting apparatus comprises a plurality of memory cells, a plurality of data lines, a plurality of bit lines, a plurality of sense amplifiers and a pre-charge control circuit.

Abstract: Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and precharging is kept to a minimum. A test DRAM cell is used to determine the exact time required for data sensing. Furthermore no precharging is performed during WRITE-operations. In case data is changing from “1” to “0” or vice versa data lines are inverted accordingly during WRITE operation.

Abstract: The invention discloses a distant PCIe extended system. The distant PCIe extended system includes a local PCIe virtualization device (PVD), at least a transmission medium and at least a remote PVD. The PVD includes a PCIe PHY layer, a signal converting circuit, at least a PVD PHY layer and a transmission medium. The PCIe PHY layer is used to receive a PCIe physical signal. The signal converting circuit is coupled to the PCIe PHY layer and used to convert the PCIe data link layer packet into at least a PVD MAC packet. The PVD PHY layer is coupled to the signal converting circuit and used to process and transfer the PVD MAC packet. The transmission medium receives and transfers the PVD physical signal.

Abstract: A chip testing circuit is disclosed. The chip testing circuit uses a judging circuit to switch the connection of the data compressing circuit between data compressing base units which compresses 4 XIOs, so as to obtain testing data by one single interface circuit and to increase the testing throughput.

Abstract: Class D amplifier is provided. The class D amplifier includes at least a block; each block includes an input circuit, an integrator, a comparator, a driving circuit and two feedback circuits. The input circuit receives a digital input to provide a differential pair of a positive and a negative input signals. The integrator receives the positive and negative input signals and a pair of positive and negative feedback signals for providing a positive error signal according to the positive input signal and the negative feedback signal, and providing a negative error signal according to the negative input signal and the positive feedback signal. The comparator compares between the positive and the negative error signals such that the driving circuit generates a driving output signal according to comparison result. The two feedback circuits respectively providing said positive and negative feedback signals according to the driving output signal.

Abstract: The invention discloses a chip testing circuit that increases the testing throughput. The chip testing circuit uses a multiplexer to switch the connection of the data compressing circuit between data compressing base units which compress 4 XIOs, so as to obtain a multiplexer of testing data by one single interface circuit and to increase the testing throughput.

Abstract: This invention provides a system in package integrated circuit with self-generating reference voltage, in which includes a logic circuit chip and a memory chip. The logic circuit chip generates a plurality of output signals, and the memory chip includes a plurality of input circuit receiving the plurality of output signals from the logic circuit chip. The memory chip further includes a voltage generator generating an input reference voltage based on an output supply voltage. The memory chip is compatible with DDR standard and the plurality of input circuit thereof is compatible with SSTL_2 standard. Wherein, each input circuit comprises a comparator with a first input terminal receiving one of the plurality of output signals and a second input terminal receiving the input reference voltage.

Abstract: Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and precharging is kept to a minimum. A test DRAM cell is used to determine the exact time required for data sensing. Furthermore no precharging is performed during WRITE-operations. In case data is changing from “1” to “0” or vice versa data lines are inverted accordingly during WRITE operation.

Abstract: The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a word line, and a second terminal. The method includes: after the memory enters the self-refreshing mode: controlling a voltage difference between the control terminal and the second terminal to correspond to a first value during a self-refreshing operation period; and controlling a voltage difference between the control terminal and the second terminal to correspond to a second value smaller than the first value during a non self-refreshing operation period.

Abstract: The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a word line, and a second terminal. The method includes: after the memory enters the self-refreshing mode: controlling a voltage difference between the control terminal and the second terminal to correspond to a first value during a self-refreshing operation period; and controlling a voltage difference between the control terminal and the second terminal to correspond to a second value smaller than the first value during a non self-refreshing operation period.

Abstract: The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a word line, and a second terminal. The method includes: after the memory enters the self-refreshing mode: controlling a voltage difference between the control terminal and the second terminal to correspond to a first value during a self-refreshing operation period; and controlling a voltage difference between the control terminal and the second terminal to correspond to a second value smaller than the first value during a non self-refreshing operation period.

Abstract: A high-tensile belt-type tag including a belt, a high-tensile transmission line, an antenna and a radio frequency identification (RFID) chip is provided, wherein the belt includes a belt body and a retaining ring. The belt body is suitable to slip into an opening of the retaining ring and preventing the belt body from slipping out of the opening. The high-tensile transmission line, the antenna and the RFID chip are disposed in the belt, and the high-tensile transmission line encircles the whole belt in accordance with a shape of the belt. Moreover, the RFID chip is coupled to the antenna through the high-tensile transmission line, wherein when the high-tensile transmission line is split as the belt is cut off, the RFID chip cannot delivers an identification code through the antenna due to split of the high-tensile transmission line.

Abstract: A DNA molecule consisting of the nucleotide sequence of SEQ ID NO: 1, which encodes a collagenous (COL1) domain and a C-terminal noncollagenous (NC1) domain of type XXI collagen. Expression systems and methods for the expression of the DNA molecule are also provided.

Abstract: The invention discloses a chip testing circuit that increases the testing throughput. The chip testing circuit uses a multiplexer to switch the connection of the data compressing circuit between data compressing base units which compress 4 XIOs, so as to obtain a multiplexer of testing data by one single interface circuit and to increase the testing throughput.

Abstract: A data detecting apparatus and a data detecting method are disclosed in the embodiments of the present invention. The data detecting apparatus operates according to a clock signal with a predetermined period. The data detecting apparatus comprises a plurality of memory cells, a plurality of data lines, a plurality of bit lines, a plurality of sense amplifiers and a pre-charge control circuit.

Abstract: A remote multiple image processing apparatus comprises a graphic processing unit, a memory unit, an image compression unit, a transmission unit and a transmission medium. The graphic processing unit receives at least an image frame including a plurality of image blocks, and determines the degree of the difference between the current input image block and the previous input image block. The memory unit, coupling to the graphic processing unit, stores the image blocks. The image compression unit, coupling to the memory unit, compresses the image blocks and generates at least a compressed datum. The transmission unit, coupling to the image compression unit, transforms the compressed datum into at least a data packet. The transmission medium outputs the data packet. The remote multiple image processing apparatus uses the compression technique to allow a client sharing the resources of graphic processing unit so as to get multiple use benefits.

Abstract: The present invention discloses a memory row architecture having memory row redundancy repair function. The memory row architecture includes a plurality of normal memory sections and a plurality of redundancy memory sections, wherein a number of the plurality of normal memory sections is more than two, a number of the plurality of redundancy memory sections is equal to the number of the plurality of normal memory sections, and a redundancy memory section is implemented in one side of each of the plurality of normal memory sections. In addition, the plurality of normal memory sections and the plurality of redundancy memory sections respectively having an odd serial number make up a first memory row redundancy repair module, and the plurality of normal memory sections and the plurality of redundancy memory sections respectively having an even serial number make up a second memory row redundancy repair module.

Abstract: The invention discloses a transmission device. The transmission device includes an interface circuit, a data converting circuit, at least a physical layer and a transmission medium. The interface circuit is used to receive a PCIe signal or a PCI signal. The data converting circuit is coupled to the interface circuit and used to convert the PCIe signal or the PCI signal into at least a data packet. The physical layer is coupled to the data converting circuit and used to process and transfer the data packet. The transmission medium receives and transfers the data packet.