Patents by Inventor Ming-Cheng Chang

Ming-Cheng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220384617
    Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Chen-Ping Chen, Kuei-Yu Kao, Shih-Yao Lin, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20220375752
    Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.
    Type: Application
    Filed: August 8, 2022
    Publication date: November 24, 2022
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen
  • Publication number: 20220367678
    Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Kai-Tai CHANG, Tung Ying LEE, Wei-Sheng YUN, Tzu-Chung WANG, Chia-Cheng HO, Ming-Shiang LIN, Tzu-Chiang CHEN
  • Publication number: 20220365428
    Abstract: Photoresist materials described herein may include various types of tin (Sn) clusters having one or more types of ligands. As an example, a photoresist material described herein may include tin clusters bearing two or more different types of carboxylate ligands. As another example, a photoresist material described herein may include tin oxide clusters that include carbonate ligands. The two or more different types of carboxylate ligands and the carbonate ligands may reduce, minimize, and/or prevent crystallization of the photoresist materials described herein, which may increase the coating performance of the photoresist materials and may decrease the surface roughness of photoresist layers formed using the photoresist materials described herein.
    Type: Application
    Filed: May 14, 2021
    Publication date: November 17, 2022
    Inventors: Ming-Hui WENG, Yahru CHENG, Ching-Yu CHANG
  • Publication number: 20220359207
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20220359709
    Abstract: A method includes forming a dummy gate electrode on a semiconductor region, forming a first gate spacer on a sidewall of the dummy gate electrode, and removing an upper portion of the first gate spacer to form a recess, wherein a lower portion of the first gate spacer remains, filling the recess with a second gate spacer, removing the dummy gate electrode to form a trench, and forming a replacement gate electrode in the trench.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 11495905
    Abstract: An electrical plug connector includes a metallic shell, a first insulated housing, a second insulated housing, a first terminal module, and a second terminal module. The first terminal module includes the first terminals and the first assembling block combined with each other to form a one-piece member, and then the first insulated housing is further combined with the first terminal module. The second terminal module includes the second terminals and the second assembling block combined with each other to form a one-piece member, and then the second insulated housing is further combined with the second terminal module. The four-piece component is assembled into the metallic shell. Accordingly, the number of the components for manufacturing the connector can be reduced, thereby simplifying the assembling procedure for the connector.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: November 8, 2022
    Assignee: ADVANCED-CONNECTEK INC.
    Inventors: Ming-Yung Chang, Tzu-Hao Li, Chia-Cheng He
  • Patent number: 11495926
    Abstract: An electrical connector assembly including an electrical connector and a circuit board is provided. The electrical connector has a metallic plate and a plurality of terminals. The metallic plate separates the terminals into two different areas. The metallic plate has a first lateral surface. The circuit board is assembled to the electrical connector. The circuit board has a plurality of pads, a second lateral surface, and top and bottom surfaces opposite to each other. The pads are disposed on the top and bottom surfaces respectively. The second lateral surface is boarded between the top and bottom surfaces. The circuit board further includes at least one grounding circuit exposed from the second lateral surface and facing toward the first lateral surface. The metallic plate is electrically conducted to the grounding circuit by the first lateral surface when the circuit board is assembled to the electrical connector.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: November 8, 2022
    Assignee: Advanced Connectek Inc.
    Inventors: Ming-Yung Chang, Tzu Hao Li, Chia Cheng He, Mao-Sheng Chen
  • Patent number: 11482421
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: October 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 11476572
    Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: October 18, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chih-Yuan Shih, Chih-Hsien Chiu, Yueh-Chiung Chang, Tsung-Li Lin, Chi-Pin Tsai, Chien-Cheng Lin, Tsung-Hsien Tsai, Heng-Cheng Chu, Ming-Fan Tsai
  • Patent number: 11476347
    Abstract: A method includes forming a dummy gate electrode on a semiconductor region, forming a first gate spacer on a sidewall of the dummy gate electrode, and removing an upper portion of the first gate spacer to form a recess, wherein a lower portion of the first gate spacer remains, filling the recess with a second gate spacer, removing the dummy gate electrode to form a trench, and forming a replacement gate electrode in the trench.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20220328646
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate including a semiconductor material. The semiconductor device includes a conduction channel of a transistor disposed above the substrate. The conduction channel and the substrate include a similar semiconductor material. The semiconductor device includes a source/drain region extending from an end of the conduction channel. The semiconductor device includes a dielectric structure. The source/drain region is electrically coupled to the conduction channel and electrically isolated from the substrate by the dielectric structure.
    Type: Application
    Filed: April 7, 2021
    Publication date: October 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chen-Ping Chen, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 11462408
    Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: October 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen
  • Publication number: 20220293528
    Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.
    Type: Application
    Filed: April 28, 2021
    Publication date: September 15, 2022
    Inventors: Shu-Cheng Chin, Ming-Yuan Gao, Chen-Yi Niu, Yen-Chun Lin, Hsin-Ying Peng, Chih-Hsiang Chang, Pei-Hsuan Lee, Chi-Feng Lin, Chih-Chien Chi, Hung-Wen Su
  • Patent number: 11444174
    Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Tai Chang, Tung Ying Lee, Wei-Sheng Yun, Tzu-Chung Wang, Chia-Cheng Ho, Ming-Shiang Lin, Tzu-Chiang Chen
  • Publication number: 20220268309
    Abstract: An eye-bolt assembly includes an eye bolt and a base portion. The eye bolt includes a ring portion, a stem portion, and at least one winged extension. The ring portion is attached a first end of the stem portion. The at least one winged extension is attached to a second end of the stem portion. The base portion receives and securely locks the eye bolt therein. The base portion includes a collar and a platform secured to the collar. The collar forms a first aperture therein. The platform forms a second aperture therein. The platform includes a spring being located at least partially within the second aperture. A first end of the spring is attached to the platform. The second aperture formed in the platform is in spaced communication with the first aperture formed in the collar.
    Type: Application
    Filed: February 23, 2021
    Publication date: August 25, 2022
    Inventors: Yaw-Tzorng TSORNG, Ming-Lung WANG, Hung-Wei CHEN, Yu-Cheng CHANG
  • Patent number: 11409062
    Abstract: Provided is an optical transceiver module, comprising a housing, a substrate, an optical receiving device and a plurality of optical transmitting devices. The substrate is disposed in the housing. The optical receiving device is disposed on the substrate. The plurality of optical transmitting devices are connected to the substrate, and the optical transmitting devices are arranged in an alternating manner. The optical transceiver module effectively utilizes the internal space thereof for a compact design and can have a simple structure for manufacturing.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: August 9, 2022
    Assignee: USENLIGHT CORPORATION
    Inventors: Chun-Yang Chang, Yun-Cheng Huang, Wen-Hsien Li, Cheng-Hung Lu, Ming-Ju Chen, Chang-Cherng Wu
  • Publication number: 20220238387
    Abstract: A method includes depositing a dummy gate dielectric layer over a semiconductor region, depositing a dummy gate electrode layer, and performing a first etching process. An upper portion of the dummy gate electrode layer is etched to form an upper portion of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper portion of the dummy gate electrode, and performing a second etching process. A lower portion of the dummy gate electrode layer is etched to form a lower portion of the dummy gate electrode. A third etching process is then performed to etch the lower portion of the dummy gate electrode using the protection layer as an etching mask. The dummy gate electrode is tapered by the third etching process. The protection layer is removed, and the dummy gate electrode is replaced with a replacement gate electrode.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20220238696
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate.
    Type: Application
    Filed: April 18, 2022
    Publication date: July 28, 2022
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 11394150
    Abstract: An electrical plug connector includes a metallic shell, a first insulated housing in the metallic shell, and a second insulated housing in the metallic shell. The first tail portions of the first terminals are divided into a first tail group and a second tail group. The second insulated housing and the first insulated housing are combined with each other. Each of the second terminals includes a second tail portion between the first tail group and the second tail group. The second tail portions and the first tail portions are aligned at a same horizontal height.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: July 19, 2022
    Assignee: ADVANCED-CONNECTEK INC.
    Inventors: Ming-Yung Chang, Tzu-Hao Li, Chia-Cheng He