Abstract: A deep trench self-alignment process for an active area of a partial vertical cell. A semiconductor substrate with two deep trenches is provided. A deep trench capacitor is formed in each deep trench, and an isolating layer is formed thereon. Each trench is filled with a mask layer. A photoresist layer is formed on the semiconductor substrate between the deep trenches, and the photoresist layer partially covers the mask layer. The semiconductor substrate is etched lower than the isolating layer using the photoresist layer and the mask layer as masks. The photoresist layer and the mask layer are removed, such that the pillar semiconductor substrate between the deep trenches functions as an active area.

Abstract: A reflective mechanism includes a base fixed on a support member of a stage lamp, a bracket fixed on the base, a mirror frame, and a reflective mirror mounted on the mirror frame. A hollow shaft rotatably extends through an axial hole of the base and includes a fork on an end thereof. The hollow shaft is driven by a first motor mounted on the base to turn about a longitudinal axis of the hollow shaft. The mirror frame includes a pivotal portion pivotally mounted to the fork of the hollow shaft. The pivotal portion of the mirror frame is driven by a second motor to pivot through transmission by an endless cord that extends through the hollow shaft without interfering with rotation of the hollow shaft.

Abstract: A reflective mechanism includes a base fixed on a support member of a stage lamp, a bracket fixed on the base, a mirror frame, and a reflective mirror mounted on the mirror frame. A hollow shaft rotatably extends through an axial hole of the base and includes a fork on an end thereof. The hollow shaft is driven by a first motor mounted on the base to turn about a longitudinal axis of the hollow shaft. The mirror frame includes a pivotal portion pivotally mounted to the fork of the hollow shaft. The pivotal portion of the mirror frame is driven by a second motor to pivot through transmission by an endless cord that extends through the hollow shaft without interfering with rotation of the hollow shaft.

Abstract: A partial vertical memory cell and fabrication method thereof. A semiconductor substrate is provided, in which two deep trenches having deep trench capacitors respectively are formed, and the deep trench capacitors are lower than a top surface of the semiconductor substrate. A portion of the semiconductor outside the deep trenches is removed to form a pillar between. The pillar is ion implanted to form an ion-doped area in the pillar corner acting as a S/D area. A gate dielectric layer and a conducting layer are conformally formed on the pillar sequentially. An isolation is formed in the semiconductor substrate beside the conducting layer. The conducting layer is defined to form a first gate and a second gate.

Abstract: A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

Abstract: A method is disclosed for making permeable artificial leather that is realistic and permeable regarding air and liquid. At first, a non-woven cloth provided. A semi-product of the artificial leather is provided by means of immersing the non-woven cloth in a solution of a polymer resin. A highly porous sheet is provided. Finally, the final product of the artificial leather is provided by means of adhering the highly porous sheet to the semi-product of the artificial leather so that gaps exist between the highly porous sheet and the semi-product of the artificial leather.

Abstract: A partial vertical memory cell and fabrication method thereof. A semiconductor substrate is provided, in which two deep trenches having deep trench capacitors respectively are formed, and the deep trench capacitors are lower than a top surface of the semiconductor substrate. A portion of the semiconductor outside the deep trenches is removed to form a pillar between. The pillar is ion implanted to form an ion-doped area in the pillar corner acting as a S/D area. A gate dielectric layer and a conducting layer are conformally formed on the pillar sequentially. An isolation is formed in the semiconductor substrate beside the conducting layer. The conducting layer is defined to form a first gate and a second gate.

Abstract: Method for preventing sneakage in shallow trench isolation and STI structure thereof. A semiconductor substrate having a pad layer and a trench formed thereon is provided, followed by the formation of a doped first lining layer on the sidewall of the trench. A second lining layer is then formed on the doped first lining layer. Etching is then performed to remove parts of the first lining layer and the second lining layer so that the height of the first lining layer is lower than the second lining layer. A sacrificial layer is then formed on the pad layer and filling the trench. Diffusion is then carried out so that the doped ions in the first lining layer out-diffuse to the substrate and form diffuse regions outside the two bottom corners of the trench.

Abstract: A double corner rounding process for a partial vertical cell. A first corner rounding process is performed after etching the substrate to form a shallow trench for device isolation. A second corner rounding process is performed after forming shallow trench isolations (STIs) and exposing the corner of the substrate at the active areas in the memory cell array region.

Abstract: A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

Abstract: A dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof. An active area comprises two vertical transistors, a common bitline contact and two deep trenches. The first vertical transistor is formed on a region where the first deep trench is partially overlapped with the first gate conductive line. The second vertical transistor is formed on a region where the second deep trench is partially overlapped with the second gate conductive line.

Abstract: An apparatus for measuring a gate oxide thickness comprises a first active area, first to fifth wordlines, first and second bar-shaped trench capacitors, and first and second gate structures. The first active area with a width of at least 2F is disposed on a substrate. The first to fifth wordline is disposed on the substrate in a first direction, with a first predetermined space between each two wordlines, and first ends of the first to fifth wordlines are electrically connected. The first and second bar-shaped trench capacitors are disposed under the second and the fourth wordlines respectively with a second predetermined space between the first and second bar-shaped trench capacitors, and F is a minimum line width of the wordlines. The first and second gate structure are respectively disposed between the first bar-shaped trench capacitor and the second wordline and between the second bar-shaped trench capacitor and the fourth wordline.

Abstract: A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.

Abstract: Method for preventing sneakage in shallow trench isolation and STI structure thereof. A semiconductor substrate having a pad layer and a trench formed thereon is provided, followed by the formation of a doped first lining layer on the sidewall of the trench. A second lining layer is then formed on the doped first lining layer. Etching is then performed to remove parts of the first lining layer and the second lining layer so that the height of the first lining layer is lower than the second lining layer. A sacrificial layer is then formed on the pad layer and filling the trench. Diffusion is then carried out so that the doped ions in the first lining layer out-diffuse to the substrate and form diffuse regions outside the two bottom corners of the trench.

Abstract: Disclosed is a deep trench structure for a semiconductor memory device. The deep trench in accordance with the present invention has a cross section communicating with two difference active areas, which are respectively connected to two adjacent bit lines of the semiconductor memory device.

Abstract: A partial vertical memory cell and fabrication method thereof. A semiconductor substrate is provided, in which two deep trenches having deep trench capacitors respectively are formed, and the deep trench capacitors are lower than a top surface of the semiconductor substrate. A portion of the semiconductor outside the deep trenches is removed to form a pillar between. The pillar is ion implanted to form an ion-doped area in the pillar corner acting as a S/D area. A gate dielectric layer and a conducting layer are conformally formed on the pillar sequentially. An isolation is formed in the semiconductor substrate beside the conducting layer. The conducting layer is defined to form a first gate and a second gate.

Abstract: A dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof. An active area comprises two vertical transistors, a common bitline contact and two deep trenches. The first vertical transistor is formed on a region where the first deep trench is partially overlapped with the first gate conductive line. The second vertical transistor is formed on a region where the second deep trench is partially overlapped with the second gate conductive line.

Abstract: A dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof. An active area comprises two vertical transistors, a common bitline contact and two deep trenches. The first vertical transistor is formed on a region where the first deep trench is partially overlapped with the first gate conductive line. The second vertical transistor is formed on a region where the second deep trench is partially overlapped with the second gate conductive line.

Abstract: An apparatus for measuring a gate oxide thickness comprises a first active area, first to fifth wordlines, first and second bar-shaped trench capacitors, and first and second gate structures. The first active area with a width of at least 2F is disposed on a substrate. The first to fifth wordline is disposed on the substrate in a first direction, with a first predetermined space between each two wordlines, and first ends of the first to fifth wordlines are electrically connected. The first and second bar-shaped trench capacitors are disposed under the second and the fourth wordlines respectively with a second predetermined space between the first and second bar-shaped trench capacitors, and F is a minimum line width of the wordlines. The first and second gate structure are respectively disposed between the first bar-shaped trench capacitor and the second wordline and between the second bar-shaped trench capacitor and the fourth wordline.

Abstract: A double corner rounding process for a partial vertical cell. A first corner rounding process is performed after etching the substrate to form a shallow trench for device isolation. A second corner rounding process is performed after forming shallow trench isolations (STIs) and exposing the corner of the substrate at the active areas in the memory cell array region.