Patents by Inventor Ming-Cheng Chang
Ming-Cheng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150374248Abstract: According to one embodiment of a device for measuring blood pressure, the device includes a pressure sensor, a microprocessor, and a user interface, wherein a user exerts pressure on the user's wrist by using the pressure sensor, the pressure sensor senses the pressure to produce oscillation signal, the microprocessor connects with the pressure sensor and receives the oscillation signal to calculate vessel pulse, systolic blood pressure, and diastolic blood pressure of the user, the user interface connects with the microprocessor and receives instruction data of the microprocessor to inform the user.Type: ApplicationFiled: June 27, 2014Publication date: December 31, 2015Inventors: Weichih Hu, Cheng-Sheng Chan, Ming-Cheng Chang
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Publication number: 20150059748Abstract: A humidifier for a respiratory apparatus includes a first cover, a second cover engaged with the first cover and a partition plate. The first cover defines an air inlet. The second cover defines a chamber configured to contain at least some amount of water. A heater is configured to heat the water to generate humidified air in the chamber. The partition plate is partly sandwiched between the first cover and the second cover. The partition plate defines an air outlet. Air input via the air inlet is humidified by being mixed with the humidified air and thereafter ejected through the air outlet. The air entering via the air inlet is divided by the partition plate into a plurality of flows having different flow velocities, thereby form a plurality of flow paths.Type: ApplicationFiled: August 14, 2014Publication date: March 5, 2015Inventors: CHIA-HSIANG HSIAO, CHIH-TSAN CHIEN, YING-CHIEH HSU, MING-CHENG CHANG, HSIN-WEI CHEN, WEN-BIN SHEN, SHU-CHI LIN, YI-CHEN LU
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Patent number: 8658538Abstract: A method of fabricating a memory device includes forming a plurality of first insulative blocks and a plurality of second insulative blocks arranged in an alternating manner in a substrate, forming a plurality of wide trenches in the substrate to form a plurality of protruding blocks, forming a word line on each sidewall of the protruding blocks, isolating the word line on each sidewall of the protruding block, and forming an trench filler in the protruding block to form two mesa structures, wherein the first insulative block and the second insulative block have different depths, and the wide trenches are transverse to the first insulative blocks.Type: GrantFiled: March 7, 2013Date of Patent: February 25, 2014Assignee: Nanya Technology CorporationInventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai
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Patent number: 8647988Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.Type: GrantFiled: March 4, 2013Date of Patent: February 11, 2014Assignee: Nanya Technology CorporationInventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai
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Patent number: 8426925Abstract: A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region.Type: GrantFiled: November 12, 2010Date of Patent: April 23, 2013Assignee: Nanya Technology Corp.Inventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai
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Patent number: 8415728Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.Type: GrantFiled: November 12, 2010Date of Patent: April 9, 2013Assignee: Nanya Technology Corp.Inventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai
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Patent number: 8368134Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.Type: GrantFiled: April 26, 2010Date of Patent: February 5, 2013Assignee: Nanya Technology CorporationInventors: Ming-Cheng Chang, Chih-Hsiung Hung, Mao-Ying Wang, Wei-Hui Hsu
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Patent number: 8334196Abstract: A method of forming a conductive contact includes forming a structure comprising an upper surface joining with a sidewall surface. The sidewall surface contains elemental-form silicon. Silicon is epitaxially grown from the sidewall surface. Dielectric material is formed over the upper surface and the epitaxially-grown silicon. A conductive contact is formed through the dielectric material to conductively connect with the upper surface.Type: GrantFiled: November 1, 2010Date of Patent: December 18, 2012Assignee: Micron Technology, Inc.Inventors: Ying-Cheng Chuang, Hung-Ming Tsai, Sheng-Wei Yang, Ping-Cheng Hsu, Ming-Cheng Chang
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Patent number: 8288231Abstract: A method of fabricating a recessed channel access transistor device is provided. First, a semiconductor substrate having thereon a recess etched into a major surface is provided. A gate dielectric layer is then formed on interior surface of the recess. A recessed gate electrode is then formed in and on the recess. The recessed gate electrode comprises a recessed gate portion that is inlaid into the recess and under the major surface, and an upper gate portion above the major surface. An exposed sidewall of the recessed gate electrode is isotropically etched to thereby form a trimmed neck portion having a width that is smaller than that of the recessed gate portion. An exposed sidewall of the trimmed neck portion is then oxidized.Type: GrantFiled: August 18, 2011Date of Patent: October 16, 2012Assignee: Nanya Technology Corp.Inventors: Wei-Ming Liao, Ming-Cheng Chang
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Publication number: 20120119277Abstract: A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region.Type: ApplicationFiled: November 12, 2010Publication date: May 17, 2012Applicant: NANYA TECHNOLOGY CORP.Inventors: YING CHENG CHUANG, PING CHENG HSU, SHENG WEI YANG, MING CHENG CHANG, HUNG MING TSAI
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Publication number: 20120119276Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.Type: ApplicationFiled: November 12, 2010Publication date: May 17, 2012Applicant: NANYA TECHNOLOGY CORP.Inventors: YING CHENG CHUANG, PING CHENG HSU, SHENG WEI YANG, MING CHENG CHANG, HUNG MING TSAI
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Publication number: 20120108047Abstract: A method of forming a conductive contact includes forming a structure comprising an upper surface joining with a sidewall surface. The sidewall surface contains elemental-form silicon. Silicon is epitaxially grown from the sidewall surface. Dielectric material is formed over the upper surface and the epitaxially-grown silicon. A conductive contact is formed through the dielectric material to conductively connect with the upper surface.Type: ApplicationFiled: November 1, 2010Publication date: May 3, 2012Inventors: Ying-Cheng Chuang, Hung-Ming Tsai, Sheng-Wei Yang, Ping-Cheng Hsu, Ming-Cheng Chang
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Patent number: 7993985Abstract: A method for forming a semiconductor device with a single-sided buried strap is provided.Type: GrantFiled: February 22, 2008Date of Patent: August 9, 2011Assignee: Nanya Technology Corp.Inventors: Neng-Tai Shih, Ming-Cheng Chang
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Patent number: 7985998Abstract: A trench-type semiconductor device structure is disclosed. The structure includes a semiconductor substrate, a gate dielectric layer and a substrate channel structure. The semiconductor substrate includes a trench having an upper portion and a lower portion. The upper portion includes a conductive layer formed therein. The lower portion includes a trench capacitor formed therein. The gate dielectric layer is located between the semiconductor substrate and the conductive layer. The substrate channel structure with openings, adjacent to the trench, is electrically connected to the semiconductor substrate via the openings.Type: GrantFiled: July 22, 2008Date of Patent: July 26, 2011Assignee: Nanya Technology Corp.Inventors: Shian-Jyh Lin, Ming-Cheng Chang, Neng Tai Shih, Hung-Chang Liao
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Patent number: 7956403Abstract: A flash memory includes a substrate with a protrusion, a control gate, two floating gates, and a dielectric layer. The protrusion extends from a top face of the substrate. The control gate is formed on the protrusion of the substrate and extendedly covers opposite sidewalls of the protrusion. The floating gates are respectively formed on top of the protrusion and being on two opposite sides of the control gate. The dielectric layer is sandwiched the control gate and each of the two floating gates. Because of the arcuate control gate used in the flash memory, the controllability of the control gate is increased and the memory cell window is enhanced.Type: GrantFiled: April 8, 2008Date of Patent: June 7, 2011Assignee: Nanya Technology CorporationInventors: Ming-Cheng Chang, Wei-Ming Liao, Jer-Chyi Wang, Yi-Feng Chang
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Publication number: 20100202468Abstract: Provided is a bridge coupled between an external host and an external storage device. The bridge includes a first interface, an encoder, a memory device, a decoder and a second interface. The first interface is coupled to the external host and receives a first data from an external host. The encoder is coupled to the first interface and compresses the first data by undistorted compression for producing a second data. The memory device is coupled to the encoder and temporally stores the second data produced by the encoder. The decoder is coupled to the memory device and decompresses the second data stored in the memory device for producing a third data. The third data and the first data are substantially the same. The second interface is coupled between the decoder and the external storage device and outputs the third data transmitted from the decoder to the external storage device.Type: ApplicationFiled: December 10, 2009Publication date: August 12, 2010Applicant: Prolific Technology Inc.Inventor: Ming-Cheng Chang
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Publication number: 20100200903Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.Type: ApplicationFiled: April 26, 2010Publication date: August 12, 2010Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Ming-Cheng Chang, Chih-Hsiung Hung, Mao-Ying Wang, Wei-Hui Hsu
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Patent number: 7754614Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.Type: GrantFiled: January 17, 2008Date of Patent: July 13, 2010Assignee: Nanya Technologies CorporationInventors: Ming-Cheng Chang, Chih-Hsiung Hung, Mao-Ying Wang, Wei-Hui Hsu
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Patent number: 7682902Abstract: A memory structure disclosed in the present invention features a control gate and floating gates being positioned in recessed trenches. A method of fabricating the memory structure includes the steps of first providing a substrate having a first recessed trench. Then, a first gate dielectric layer is formed on the first recessed trench. A first conductive layer is formed on the first gate dielectric layer. After that, the first conductive layer is etched to form a spacer which functions as a floating gate on a sidewall of the first recessed trench. A second recessed trench is formed in a bottom of the first recessed trench. An inter-gate dielectric layer is formed on a surface of the spacer, a sidewall and a bottom of the second recessed trench. A second conductive layer formed to fill up the first and the second recessed trench.Type: GrantFiled: December 4, 2007Date of Patent: March 23, 2010Assignee: Nanya Technology Corp.Inventors: Ching-Nan Hsiao, Pei-Ing Lee, Ming-Cheng Chang, Chung-Lin Huang, Hsi-Hua Chang, Chih-Hsiang Wu
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Patent number: 7642142Abstract: A method for forming a semiconductor device includes providing a substrate and forming conductor patterns and openings on the substrate. Next the openings are filled with a mask layer and upper portions of the conductor patterns are etched to form cavities. Following, a portion of the mask layer is removed to form a trench between two neighboring conductor patterns, wherein the trench exposes the substrate and the sidewalls of the two neighboring conductor patterns. Next, an insulating layer on the cavities and the trench is conformably formed, a second conductive layer is formed on the insulating layer and the trench is filled with the second conductive layer.Type: GrantFiled: January 17, 2008Date of Patent: January 5, 2010Assignee: Nanya Technology CorporationInventors: Wei-Ming Liao, Ming-Cheng Chang