Abstract: An LED tube lamp includes a first and second members and a connection member. Each of the first and second members includes lighting part and an end part. Each lighting part includes LED light strip. The connection member includes electrical connection portions and joining portions for the first and second members. The connection member connects the first member with the second member by the joining portions and the electrical connection portions and makes the first member substantially coaxial to the second member.

Abstract: An imaging lens assembly module includes an imaging lens element set, a lens carrier and a light blocking structure. The imaging lens element set has an optical axis. At least one lens element of the lens elements is disposed in the lens carrier. The light blocking structure includes a light blocking opening. The optical axis passes through the light blocking opening, and the light blocking opening includes at least two arc portions and a shrinking portion. Each of the arc portions has a first curvature radius for defining a maximum diameter of the light blocking opening. The shrinking portion is connected to the arc portions for forming the light blocking opening into a non-circular shape. The shrinking portion includes at least one protruding arc which extends and shrinks gradually from the shrinking portion to the optical axis, and the protruding arc has a second curvature radius.

Abstract: A method for locating critical control points on a part or combination of parts during a manufacturing process involves mating, directly or indirectly, a jig extension to the part or parts. A pattern on the jig extension defines an origin point that is used to track the position of the part or parts during manufacturing, such as during location-sensitive operations. The jig extension may be a shoe last extension which connects to a shoe or shoe component via a shoe last.

Abstract: A manufacturing method of a semiconductor structure is provided. A first semiconductor die includes a first semiconductor substrate, a first interconnect structure formed thereon, a first bonding conductor formed thereon, and a conductive via extending from the first interconnect structure toward a back surface of the first semiconductor substrate. The first semiconductor substrate is thinned to accessibly expose the conductive via to form a through semiconductor via (TSV). A second semiconductor die is bonded to the first semiconductor die. The second semiconductor die includes a second semiconductor substrate including an active surface facing the back surface of the first semiconductor substrate, a second interconnect structure between the second and the first semiconductor substrates, and a second bonding conductor between the second interconnect structure and the first semiconductor substrate and bonded to the TSV.

Abstract: A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.

Abstract: The present disclosure is directed to systems and methods of improving the thermal performance of processor-based devices. Such thermal performance improvement may include limiting the degree of tilt experienced by a semiconductor device as a thermal solution coupled to the semiconductor device is tightened to the substrate. Such thermal performance improvements may include increasing the available heat transfer area associated with a particular heat producing semiconductor device. Such thermal performance improvements may include thermally coupling one or more cool blocks thermally coupled to one or more remote heat-producing devices to a central cool block that may be cooled using a cooling medium or coupled to a central heat-producing semiconductor device.

Abstract: An imaging lens assembly has an optical axis, and includes a plastic carrier element and an imaging lens element set. The plastic carrier element includes an object-side surface, an image-side surface, an outer surface and an inner surface. The object-side surface includes an object-side opening. The image-side surface includes an image-side opening. The inner surface is connected to the object-side opening and the image-side opening. The imaging lens element set is disposed in the plastic carrier element, and includes at least three lens elements, each of at least two adjacent lens elements of the lens elements includes a first axial assembling structure, the first axial assembling structures are corresponding to and connected to each other. A solid medium interval is maintained between the adjacent lens elements and the inner surface. The solid medium interval is directly contacted with the adjacent lens elements and the inner surface.

Abstract: An electronic device includes a casing, a driven component, a magnetic component and an electromagnetic component. The casing has an outer surface, an inner surface, and an accommodating groove penetrating through the outer surface and the inner surface. The driven component is movably disposed in the accommodating groove. The magnetic component is connected to the driven component. The electromagnetic component is aligned with the magnetic component, and the magnetic component and the electromagnetic component are located at the same side of the inner surface. When the electromagnetic component isn't powered, the magnetic component and the electromagnetic component are attracted to each other, and the driven component is positioned at a first position. When the electromagnetic component is powered, the magnetic component and the electromagnetic component are repulsed to each other so as to drive the driven component to move from the first position to the second position.

Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

Abstract: A laser grooving operation is performed to form a plurality of grooves in a semiconductor die prior to attaching the semiconductor die to a semiconductor device package substrate. In addition to forming a first groove through which blade sawing is to be performed to separate the semiconductor die from other semiconductor dies, a second groove may be formed between the first groove and a seal ring of the semiconductor die. The second groove is configured to contain any potential delamination that might otherwise propagate to an active region of the semiconductor die. Accordingly, the second groove and the associated laser grooving operation described herein may reduce the likelihood of delamination that might otherwise be caused by swelling and/or expansion in a molding compound formed around the semiconductor die after the semiconductor die is attached to the semiconductor device package substrate.

Abstract: A device stand may include a base having a support portion and a connector portion. An upper surface of the connector portion may include at least one coupling mechanism that is configured to engage with a corresponding feature of a keyboard housing to secure the base with the keyboard housing. The device stand may include a first support member coupled with the support portion. The device stand may include a second support member coupled with the support portion and laterally spaced apart from the first support member to form a channel between the first support member and the second support member. The channel may be sized to receive a computing device.

Abstract: Manufacturing of a shoe is enhanced by creating 3-D models of shoe parts. For example, a laser beam may be projected onto a shoe-part surface, such that a projected laser line appears on the shoe part. An image of the projected laser line may be analyzed to determine coordinate information, which may be converted into geometric coordinate values usable to create a 3-D model of the shoe part. Once a 3-D model is known and is converted to a coordinate system recognized by shoe-manufacturing tools, certain manufacturing steps may be automated.

Abstract: An electronic device includes a storage array, a row fan, a distance sensor, and a controller. The storage array includes a plurality of storage units. The row fan cools the storage array. The distance sensor senses the distance between the storage array and the row fan and outputs a corresponding distance signal. The controller receives the distance signal and sets the distance threshold of each of the storage units. When the distance is longer than the distance threshold, the controller outputs a control signal to the row fan to increase the rotation speed of the row fan.

Abstract: An overlay mark includes a first feature extending in an X-direction, wherein the first feature is a first distance from a substrate. The overlay mark further includes a second feature extending in a Y-direction perpendicular to the X-direction, wherein the second feature is a second distance from the substrate, and the second distance is different from the first distance, wherein at least one of the first feature or the second feature comprises a conductive material. The overlay mark further includes a third feature extending in the X-direction and the Y-direction, wherein the third feature is a third distance from the substrate, and the third distance is different from the first distance and the second distance. The first distance, the second distance and the third distance from the substrate are along a Z-direction perpendicular to both the X-direction and the Y-direction.

Abstract: In a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, one or more first resist layers are formed over the hard mask layer, a first photo resist pattern is formed over the one or more first resist layers, a width of the first photo resist pattern is adjusted, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer is patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.

Abstract: The present disclosure describes a structure that joins semiconductor packages and a method for forming the structure. The structure includes an adhesion layer in contact with a first semiconductor package and a first joint pad in contact with the adhesion layer. The structure further includes a film layer disposed on the first semiconductor package and the first joint pad, where the film layer includes a slanted sidewall, the slanted sidewall covers an end portion of the adhesion layer and a first portion of the first joint pad, and the slanted sidewall exposes a second portion of the first joint pad. The structure further includes a solder ball attached to the second portion of the first joint pad and a second joint pad of a second semiconductor package.

Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a patterning process; and forming a second plurality of trenches in the first layer by another patterning process, resulting in combined trench patterns in the first layer. A first trench of the second plurality connects two trenches of the first plurality. The method further includes forming dielectric spacer features on sidewalls of the combined trench patterns. A space between two opposing sidewalls of the first trench is completely filled by the dielectric spacer features and another space between two opposing sidewalls of one of the two trenches is partially filled by the dielectric spacer features.

Abstract: A method for locating critical control points on a part or combination of parts during a manufacturing process involves mating, directly or indirectly, a jig extension to the part or parts. A pattern on the jig extension defines an origin point that is used to track the position of the part or parts during manufacturing, such as during location-sensitive operations. The jig extension may be a shoe last extension which connects to a shoe or shoe component via a shoe last.

Abstract: The present disclosure provides a hybrid powertrain system, comprising: an engine; a motor/generator (“MG”); a clutch coupled to the engine and the MG; a transmission coupled to the MG; an energy storage system connected to the MG; and a controller coupled to the engine, the MG, the clutch, the transmission and the energy storage system. The controller is configured to initiate an engine stop, allow engine torque and MG torque to reduce to zero or near zero, shift the transmission to a neutral gear, cause the MG to operate in a generator mode, thereby loading the engine to recover kinetic energy from the engine, disengage the clutch to decouple the MG from the engine, increase the speed of the MG to a target speed, and shift the transmission into gear in response to the MG reaching the target speed.