Patents by Inventor Ming Feng

Ming Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11431185
    Abstract: A device including a first receptacle for receiving a first electronic device, a second receptacle for receiving a second electronic device, a first switching charger for fast charging the first electronic device, and a second switching charger for fast charging the second electronic device. The device may determine that the first electronic device is communicatively coupled to the device within the first receptacle and that the second electronic device is communicatively coupled to the device within the second receptacle. The device may receive a first request from the first electronic device to fast charge the first electronic device via the first switching charger and charge the first electronic device via the first switching charger. Additionally, the device may receive a second request from the second electronic device to fast charge the second electronic device via the second switching charger and charge the second electronic device via the second switching charger.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: August 30, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Ming Feng, Benjamin Gaide
  • Publication number: 20220252390
    Abstract: Manufacturing of a shoe is enhanced by creating 3-D models of shoe parts. For example, a laser beam may be projected onto a shoe-part surface, such that a projected laser line appears on the shoe part. An image of the projected laser line may be analyzed to determine coordinate information, which may be converted into geometric coordinate values usable to create a 3-D model of the shoe part. Once a 3-D model is known and is converted to a coordinate system recognized by shoe-manufacturing tools, certain manufacturing steps may be automated.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 11, 2022
    Inventors: Patrick C. Regan, Chih-Chi Chang, Kuo-Hung Lee, Ming-Feng Jean
  • Publication number: 20220245293
    Abstract: A tool path for treating a shoe upper may be generated to treat substantially only the surface of the shoe bounded by a bite line. The bite line may be defined to correspond to the junction of the shoe upper and a shoe bottom unit. Bite line data and three-dimensional profile data representing at least a portion of a surface of a shoe upper bounded by a bite line may be utilized in combination to generate a tool path for processing the surface of the upper, such as automated application of adhesive to the surface of a lasted upper bounded by a bite line.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 4, 2022
    Inventors: Patrick Conall Regan, Dragan Jurkovic, Chih-Chi Chang, Ming-Feng Jean
  • Patent number: 11404128
    Abstract: A power control method for a memory storage device and a memory storage system are provided. The method includes configuring a power controller in a host system, controlling, by the power controller, a power gate disposed between the host system and the memory storage device, and controlling a power supply of the memory storage device from the host system by the power gate, wherein the power gate is not controlled by a Basic Input Output System (BIOS) controller of the host system.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: August 2, 2022
    Assignee: ACER INCORPORATED
    Inventors: Guan-Yu Hou, Tz-Yu Fu, Chun-Chih Kuo, Ming Feng Hsieh
  • Patent number: 11404413
    Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, insulators, gate stacks, and first and second S/Ds. The first and second regions respectively includes at least one first semiconductor fin and at least one second semiconductor fin. A width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin. A width of a middle portion of the second semiconductor fin is smaller than widths of end portions of the second semiconductor fin. The insulators are disposed on the semiconductor substrate. The first and second semiconductor fins are sandwiched by the insulators. The gate stacks are over a portion of the first semiconductor fin and a portion of the second semiconductor fin. The first and second S/Ds respectively covers another portion of the first semiconductor fin and another portion of the second semiconductor fin.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Jung Chen, I-Chih Chen, Chih-Mu Huang, Kai-Di Wu, Ming-Feng Lee, Ting-Chun Kuan
  • Publication number: 20220234868
    Abstract: A buffer type speed difference falling protector includes a shell, a speed difference falling protector body and a speed difference falling protector body, wherein the shell is provided with an opening; the frame body is arranged in the shell; the winding device is arranged on the frame body, can wind the rope body when the winding device rotates in the forward direction, and releases the rope body when the winding device rotates in the reverse direction; and the elastic resetting piece is used for driving the winding device to rotate in the positive direction. The plurality of pawls are arranged on the fixing piece, when the braking device rotates, the plurality of pawls are thrown out synchronously to be contacted with the ratchets, the braking speed is high, the braking reliability is high, and the plurality of pawls can equally divide the impact force during braking.
    Type: Application
    Filed: April 7, 2022
    Publication date: July 28, 2022
    Applicants: JINHUA JECH TOOLS CO., LTD, JINHUA JECH TOOLS CO., LTD
    Inventor: Ming Feng
  • Publication number: 20220223727
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Application
    Filed: January 27, 2022
    Publication date: July 14, 2022
    Inventors: Shao-Ming YU, Chang-Yun CHANG, Chih-Hao CHANG, Hsin-Chih CHEN, Kai-Tai CHANG, Ming-Feng SHIEH, Kuei-Liang LU, Yi-Tang LIN
  • Patent number: 11387105
    Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
  • Patent number: 11382391
    Abstract: A method for locating critical control points on a part or combination of parts during a manufacturing process involves mating, directly or indirectly, a jig extension to the part or parts. A pattern on the jig extension defines an origin point that is used to track the position of the part or parts during manufacturing, such as during location-sensitive operations. The jig extension may be a shoe last extension which connects to a shoe or shoe component via a shoe last.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: July 12, 2022
    Assignee: NIKE, Inc.
    Inventors: Dragan Jurkovic, Ming-Feng Jean, Chin-Yi Lin, Chun-Chi Lin
  • Patent number: 11384700
    Abstract: Control of a spark ignited internal combustion in response to an exhaust manifold pressure measurement of an engine is disclosed. An engine out NOx amount for at least one cylinder is determined at least in part in response to the exhaust manifold pressure measurement and a brake mean effective pressure of the at least one cylinder. An operating condition of the engine is adjusted in response to the engine out NOx amount.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: July 12, 2022
    Assignee: Cummins Inc.
    Inventors: Ming-Feng Hsieh, Andrew G. Kitchen, Axel Otto zur Loye, Jinghua Zhong, Richard A. Booth, Robert J. Thomas, Jisang Sun
  • Patent number: 11378026
    Abstract: A spark ignited internal combustion engine is controlled in response to a self-learned TOB reference. The self-learned TOB reference is based on a difference between a learned TOB offset and a desired or target TOB, and a sensed TOB. The learned TOB offset at a given operating condition, such as charge pressure, can be found by interpolating between the learned charge pressure breakpoints in a TOB learning algorithm. The TOB learning algorithm can include using a filtered charge pressure value to indicate the engine load at which the TOB is learned. An index determination is made with a look up table with charge pressure as an input and an array index of learned charge pressure and learned TOB offset as outputs.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: July 5, 2022
    Assignee: Cummins Inc.
    Inventors: Omkar A. Harshe, Ming-Feng Hsieh
  • Patent number: 11360524
    Abstract: An electronic device includes a first body, a second body, two hinges, and at least one electronic assembly. The two hinges are connected between the first body and the second body, and the first body and the second body are adapted to rotate relatively through the two hinges. The electronic assembly is connected to the second body and is located between the two hinges.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: June 14, 2022
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Ming-Chung Peng, Ko-Fan Chen, Chun-Yi Ho, Chien-Ting Lin, Yu-Jung Liu, Hsin-Jung Lee, Hsin-Yu Huang, Jih-Houng Lee, Ming-Feng Liu, Kuo-Jung Wu, Kuo-Pin Chen, Chia-Ling Lee, Jing-Jie Lin
  • Patent number: 11346654
    Abstract: Manufacturing of a shoe is enhanced by creating 3-D models of shoe parts. For example, a laser beam may be projected onto a shoe-part surface, such that a projected laser line appears on the shoe part. An image of the projected laser line may be analyzed to determine coordinate information, which may be converted into geometric coordinate values usable to create a 3-D model of the shoe part. Once a 3-D model is known and is converted to a coordinate system recognized by shoe-manufacturing tools, certain manufacturing steps may be automated.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: May 31, 2022
    Assignee: NIKE, Inc.
    Inventors: Patrick C. Regan, Chih-Chi Chang, Kuo-Hung Lee, Ming-Feng Jean
  • Patent number: 11338449
    Abstract: Systems, apparatus, and methods of manufacturing an article using electroadhesion technology for the pick-up and release of materials, respectively.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: May 24, 2022
    Assignee: Grabit, Inc.
    Inventors: Harsha Prahlad, Richard J. Casler, Susan Kim, Matthew Leettola, Jon Smith, Kenneth Tan, Patrick Wang, John Mathew Farren, Patrick Conall Regan, Po Cheng Chen, Howard Fu, Dragan Jurkovic, Aishwarya Varadhan, Chang-Chu Liao, Chih-Chi Chang, Kuo-Hung Lee, Ming-Feng Jean
  • Patent number: 11341291
    Abstract: A tool path for treating a shoe upper may be generated to treat substantially only the surface of the shoe bounded by a bite line. The bite line may be defined to correspond to the junction of the shoe upper and a shoe bottom unit. Bite line data and three-dimensional profile data representing at least a portion of a surface of a shoe upper bounded by a bite line may be utilized in combination to generate a tool path for processing the surface of the upper, such as automated application of adhesive to the surface of a lasted upper bounded by a bite line.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: May 24, 2022
    Assignee: NIKE, Inc.
    Inventors: Patrick Conall Regan, Dragan Jurkovic, Chih-Chi Chang, Ming-Feng Jean
  • Publication number: 20220151345
    Abstract: Manufacturing and assembly of a shoe or a portion of a shoe is enhanced by automated placement and assembly of shoe parts. For example, a part-recognition system analyzes an image of a shoe part to identify the part and determine a location of the part. Once the part is identified and located, the part can be manipulated by an automated manufacturing tool.
    Type: Application
    Filed: January 28, 2022
    Publication date: May 19, 2022
    Inventors: Patrick Conall Regan, Kuo-Hung Lee, Chih-Chi Chang, Ming-Feng Jean, Chang-Chu Liao
  • Publication number: 20220139922
    Abstract: A memory device includes a first electrode, a first support layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate and extending upwards. The first support layer laterally supports an upper portion of a sidewall of the first electrode, where the first support layer has a slim portion. The dielectric layer is disposed on the first electrode and the first support layer. The second electrode is disposed on the dielectric layer. In addition, a method of fabricating the memory device is provided.
    Type: Application
    Filed: August 17, 2021
    Publication date: May 5, 2022
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Wang Jhan, Yu-Cheng Tung, Fu-Che Lee, Chien-Cheng Tsai, An-Chi Liu, Ming-Feng Kuo, Gang-Yi Lin, JUNYI ZHENG
  • Patent number: 11307447
    Abstract: A display device including a display panel having a top surface, a side surface, a light shielding component, and an optical film is provided. The side surface is adjacent to the top surface. The light shielding component has a first part and a second part. The first part is disposed on the top surface of the display panel. The second part is disposed on the side surface of the display panel. The optical film at least covers the border between the top surface of the display panel and the first part of the light shielding component. The width of the first part of the light shielding component is less than 1 mm.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: April 19, 2022
    Assignee: INNOLUX CORPORATION
    Inventors: Yung-Chih Chen, Ming-Feng Hsieh, Yen-Shuo Chen, Chung-Cheng Huang
  • Publication number: 20220102274
    Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.
    Type: Application
    Filed: June 10, 2021
    Publication date: March 31, 2022
    Inventors: Hung-Chung Chien, Chao-Hong Chen, Ming-Feng Shieh
  • Publication number: 20220100103
    Abstract: Semiconductor processing apparatuses and methods are provided in which a semiconductor wafer is flipped and then rotated between patterning of front and back sides of the semiconductor wafer by first and second reticles, respectively. In some embodiments, a method includes patterning, by a first reticle, a first layer on a first side of a semiconductor wafer while the first side of the semiconductor wafer is facing a first direction. The semiconductor wafer is then flipped. A second side of the semiconductor wafer that is opposite the first side faces the first direction after the flipping the semiconductor wafer. The semiconductor wafer is then rotated about a rotational axis extending along the first direction, and a second layer on the second side of the semiconductor wafer is patterned by a second reticle.
    Type: Application
    Filed: March 10, 2021
    Publication date: March 31, 2022
    Inventors: Hung-Chung CHIEN, Hao-Ken HUNG, Chih-Chieh YANG, Ming-Feng SHIEH, Chun-Ming HU