Abstract: A silicon nitride read only memory and associated method of data programming and erasing. The read only memory includes a first type ion-doped semiconductor substrate, an oxide-nitride-oxide (ONO) composite layer over the semiconductor substrate, a first type ion-doped gate conductive layer over the ONO layer and a second type ion doped source/drain region in the substrate on each side of the ONO layer, wherein the second type ions have an electrical polarity opposite to the first type ions. Data is programmed into the silicon nitride read only memory by channel hot electron injection and data is erased from the silicon nitride read only memory by negative gate channel erase method. Since the gate conductive layer and the channel layer are identically doped, the energy gap between the two layers reduced. Hence, operating voltage of the gate terminal is lowered and damage to the tunnel oxide layer by hot holes is reduced.

Abstract: The present invention provides a memory array fabricated by complementary metal-oxide-semiconductor salicide process. The memory array comprises a semiconductor substrate. Multitudes of first isolation devices are aligned in the semiconductor substrate and second isolation devices aligned on the semiconductor substrate. The alignment of the second isolation devices is parallel to one of the first isolation devices. Some polysilicon lines are on the second isolation devices therefor have null memory function. A conductive structure is below a surface of the semiconductor substrate. The conductive structure is located between the first isolation devices. A conductive contact is on the conductive structure. The correspondence of the first isolation devices and the polysilicon lines can prevent the conductive structures from short effect.

Abstract: An flash memory erase method. A bias Vg is applied to a gate of a memory cell. A bias Vd is applied to a source/drain region of the memory cell to execute an erase operation. The bias Vd is increased from an initial value to a predetermined value over time. During the increase of the bias Vd, no inspection is performed. Whether the memory of each memory cell has been erased is inspected. If the erase operation is complete, the erase operation is over. If not, a voltage raise erase-inspection step is performed at least once until it is confirmed that the memory of all the memory cells has been erase. Each voltage raise erase-inspection step includes an erase step with a raised voltage and an inspection step afterwards.

Abstract: A method of stabilizing a reference bit of a multi-bit memory cell. A first bit of a multi-bit memory cell is pre-programmed to high during fabrication. While reading the multi-bit memory cell, another bit other than the first bit is read as a reference bit.

Abstract: The present invention provides a protection circuit comprising one diode wherein the diode is formed by diffusing a heavily doped material of a first conductivity type into a first region of a second conductivity type. An integrated circuit, such as a memory array, is coupled to the diode. The other diode back-to-back is coupled to the diode wherein the other diode is formed by diffusing a heavily doped material of the second conductivity type into the first region and a second region of the first conductivity type. The two diodes in series are capable of discharging for the memory array during manufacturing process.

Abstract: A random access memory cell. The RAM cell includes a first transistor and a second transistor. A control gate of the first transistor is coupled to a control signal line. A data read terminal of the first transistor is coupled to a data read line. An earth terminal of the first transistor is connected to a ground. A floating gate terminal of the first transistor is located between a portion of a substrate and a portion of the control gate. A control gate of the second transistor is also coupled to the control signal line. The data write terminal of the second transistor is a data write line. A data transmission terminal of the second transistor is coupled to the floating gate of the first transistor. To write data into the RAM cell, a write control voltage is applied to the control signal line. Similarly, to read data from the RAM cell, a read control voltage is applied to the control signal line. The write control voltage is greater than the read control voltage.

Abstract: A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.

Abstract: A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.