Abstract: Examples of an exercise mat and methods for making same are disclosed. The exercise mat comprises a top layer, at least two textured gripping zones formed on an upper surface of the top layer and a bottom layer joined to the top layer. A second textured gripping zone of the at least two textured gripping zones may be formed closer to one or more mat edges of the exercise mat, and has a friction level that is greater than a friction level of a first textured gripping zone of the at least two textured gripping zones, when a body is in sliding contact with the at least two textured gripping zones of the upper surface of the top layer.

Abstract: A circuit board module including a circuit board body, a connector, and a release component is provided. The connector is disposed on the circuit board body and includes a base body and a rotating button rotatably disposed on the base body. The release component is disposed on the circuit board body and includes a linking member. The linking member is movably disposed beside the rotating button and does not contact the rotating button under normal conditions. When an external force triggers the release component, the linking member is driven to contact the rotating button, so that the rotating button rotates relative to the base body. In addition, a release component is also mentioned.

Abstract: A circuit board module includes a circuit board body, a connector, a press button, a bracket, and a linkage. The connector includes a base and a rotating button rotatably disposed on the base. The press button is located away from the connector. The bracket includes a first limiting portion. The linkage is located between the rotating button and the press button and includes a second limiting portion corresponding to the first limiting portion, a first segment, and a second segment linked to the first segment. The first segment extends along a first axis and is linked to the rotating button. The second segment extends along a second axis and is linked to the press button. One of the second limiting portion and the first limiting portion extends along the first axis. The first segment is movably disposed on the bracket along the first axis.

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

Abstract: The present disclosure provides high strength, self-ligating appliances with orthodontically desirable dimensions. The appliances of the present disclosure incorporate a door slidably engaged to a channel in the body; one that can be opened or closed depending on the equilibrium position of an integral protrusion on the door. Cooperating grooves and rails on the body and the door can guide the door between the open and closed positions and mitigate against unintentional detachment.

Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

Abstract: The present disclosure provides a motor including a stator, a rotor and a first circuit board. The stator includes a winding assembly including a plurality of coils. A conductive element is extended out from the winding assembly and is electrically connected to a first electrical connector. The first electrical connector penetrates through a pillow of the stator and is electrically connected to the first circuit board. The motor further includes a second circuit board, and the second circuit board is electrically connected to the first circuit board. The first electrical connector serves as a connector for electrically connecting the winding assembly to the first circuit board. The present disclosure has the advantage of easy installation by replacing the conventional wire binding plate with the first circuit board.

Abstract: In an embodiment, a method (of manufacturing fins for a semiconductor device) includes: forming a first layer (on a semiconductor substrate) that has first spacers and etch stop layer (ESL) portions which are interspersed; forming second spacers on central regions of the first spacers and the ESL portions; removing exposed regions of the first spacers and the ESL portions and corresponding underlying portions of the semiconductor substrate; removing the second spacers resulting in corresponding first capped semiconductor fins and second capped semiconductor fins that are organized into first and second sets; each member of the first set having a first cap with a first etch sensitivity; and each member of the second set having a second cap with a different second etch sensitivity; and eliminating selected ones of the first capped semiconductor fins and selected ones of the second capped semiconductor fins.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.

Abstract: An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.

Abstract: The present disclosure provides an optical module. The optical module includes an optical component disposed in or on a carrier and configured to receive a first light. The optical component is further configured to transmit a second light to a first portion of the carrier and transmit a third light to a second portion of the carrier.

Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface; a semiconductor die mounted on the top surface of the substrate; and a two-part lid mounted on a perimeter of the top surface of the substrate and housing the semiconductor die. The two-part lid comprises an annular lid base and a cover plate removably installed on the annular lid base.

Abstract: The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a substrate, a first electronic component and a support component. The first electronic component is disposed on the substrate. The first electronic component has a backside surface facing a first surface of the substrate. The support component is disposed between the backside surface of the first electronic component and the first surface of the substrate. The backside surface of the first electronic component has a first portion connected to the support component and a second portion exposed from the support component.

Abstract: A semiconductor device package includes a light-emitting device, a diffuser structure, a first optical sensor, and a second optical sensor. The light-emitting device has a light-emitting surface. The diffuser structure is above the light-emitting surface of the light-emitting device. The first optical sensor is disposed below the diffuser structure, and the first optical sensor is configured to detect a first reflected light reflected by the diffuser structure. The second optical sensor is disposed below the diffuser structure, and the second optical sensor is configured to detect a second reflected light reflected by the diffuser structure.

Abstract: A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

Abstract: A hybrid metal-oxide semiconductor field-effect transistor with variable gate impedance and an implementation method thereof, wherein the hybrid metal-oxide semiconductor field-effect transistor has the characteristic of changing the on-resistance according to different drive voltages. By use of a feedback loop and a variable gate drive voltage generator which can vary the generated gate drive voltage based on different loads, the present disclosure can still adjust the gate drive voltage under different load conditions without requiring a plurality of metal-oxide semiconductor field-effect transistors in series/parallel to achieve the lowest power loss.

Abstract: A metal-oxide semiconductor field-effect transistor with asymmetric parallel die and an implementation method thereof, comprising an inductor, a load recognition control unit and a metal-oxide semiconductor field-effect transistor having a first die, a second die, and a switch. The first die is larger in size than the second die. The inductor can produce a voltage signal when the load changes. The switch is controlled by the load recognition control unit such that different dies are switched on under different load conditions, thereby improving efficiency under light load condition in addition to reducing volume and cost.

Abstract: A dual sensor imaging system and an imaging method thereof are provided. The method includes: identifying an imaging scene; controlling a color sensor and an IR sensor to respectively capture color images and IR images by adopting capturing conditions suitable for the imaging scene; calculating a signal-to-noise ratio (SNR) difference between each color image and the IR images, and a luminance mean value of each color image; selecting the color image and IR image captured under capturing conditions of having the SNR difference less than an SNR threshold and the luminance mean value greater than a luminance threshold to execute a feature domain transformation to extract partial details of the imaging scene; and fusing the selected color image and IR image to adjust the partial details of the color image according to a guidance of the partial details of the IR image to obtain a scene image with full details.