Abstract: A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

Abstract: A dual sensor imaging system and a depth map calculation method thereof are provided. The dual sensor imaging system includes at least one color sensor, at least one infrared ray (IR) sensor, a storage device, and a processor. The processor is configured to load and execute a computer program stored in the storage device to: control the color sensor and the IR sensor to respectively capture multiple color images and multiple IR images by adopting multiple exposure conditions suitable for an imaging scene, adaptively select a combination of the color image and the IR image that are comparable to each other from the color images and the IR images; and calculate a depth map of the imaging scene by using the selected color image and IR image.

Abstract: A dual sensor imaging system and an imaging method thereof are provided. The dual sensor imaging system includes at least one color sensor, at least one infrared ray (IR) sensor, a storage device, and a processor. The processor is configured to load and execute a computer program stored in the storage device to: identify an imaging scene of the dual sensor imaging system; control the color sensor and the IR sensor to respectively capture multiple color images and multiple IR images by adopting multiple exposure conditions suitable for the imaging scene; adaptively select a combination of the color image and the IR image that can reveal details of the imaging scene; and fuse the selected color image and IR image to generate a scene image with details of the imaging scene.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a semiconductor package device, a first constraint structure and a second constraint structure. The first constraint structure is connected to the semiconductor package device. The second constraint structure is connected to the semiconductor package device and under a projection of the semiconductor package device.

Abstract: Continuous adjustment appliances are provided that can store a large number of geometries that can be successively accessed throughout orthodontic treatment, with each geometry can correspond to an arrangement of the patient's teeth. An appliance according to the present disclosure can be stimulated to transition among the myriad geometries, which can include changes to the overall shape of the appliance as well as the position and geometry of the cavities corresponding to a patient's teeth. Methods of creating the continuous adjustment appliances and methods of treatment using the continuous adjustment appliances are also revealed.

Abstract: A method of manufacturing an integrated circuit (IC) structure includes forming an opening in a first dielectric material between a first gate structure and a second gate structure by removing a portion of the first dielectric material overlying a fin structure; filling at least part of the opening with a second dielectric material; and forming a contact overlying the fin structure and the second dielectric material.

Abstract: A casing assembly having at least one configuration for blocking extraneous material and including first shell part and second shell part. First shell part includes contact portion and first recess portion. Second shell part includes step portion and protrusion portion. Step portion is in contact with contact portion of first shell part and forms decorative slot exposed to outside with contact portion. First recess portion is located on side of contact portion that is located away from decorative slot. Protrusion portion is located on side of step portion that is located away from decorative slot and located in first recess portion. Protrusion portion has top surface facing toward first recess portion, first recess portion has bottom surface, and idle cavity is formed between top surface of protrusion portion and bottom surface of first recess portion.

Abstract: The present disclosure provides a motor including a base, a stator and a rotor. The stator is disposed on the base. The base includes a cylinder. There is a flange disposed on a side of the cylinder neighboring to the rotor. Fins are axially disposed on the flange, and the periphery of the flange has a breach. The breach is partially extended to the cylinder, and there is also a plurality of fins disposed in the breach. A plurality of air-guiding members are annularly disposed on the periphery of the rotor. The air-guiding members are connected to each other through a connecting rim. The fins on the flange and the air-guiding members of the rotor are both extended axially, thus the interference therebetween is avoided. When the motor rotates, the air-guiding members are able to drive the flow passing through the breach for achieving heat-dissipating effect.

Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer has a trench. The method includes forming a first spacer and a second spacer respectively over opposite inner walls of the trench. The first spacer and the second spacer are spaced apart from each other. The method includes removing a first portion of the first spacer to form a first gap in the first spacer, wherein a first part and a second part of the first spacer are spaced apart by the first gap, and the first gap communicates with the trench. The method includes forming a filling layer into the trench and the first gap to cover the first spacer and the second spacer. The filling layer, the first spacer, and the second spacer together form a strip structure. The method includes removing the first layer.

Abstract: A sensing module, a semiconductor device package and a method of manufacturing the same are provided. The sensing module includes a sensing device, a first protection film and a second protection film. The sensing device has an active surface and a sensing region disposed adjacent to the active surface of the sensing device. The first protection film is disposed on the active surface of the sensing device and fully covers the sensing region. The second protection film is in contact with the first protection film and the active surface of the sensing device.

Abstract: Investigation of fine tissue structures, such as those in non-neural, non-osseous tissues or organs, is best performed in intact tissue. Described herein are compositions and methods for clearing tissues for subsequent three-dimensional analysis. The compositions referred to herein as tissue clearing compositions are composed of four core components: (1) a homogenizing agent such as N-methylglucamine, urea, thiourea, guanidine, guanidinium chloride, lithium perchlorate, ethylenediamine, and derivatives thereof; (2) a water-soluble adjusting agent such as iohexol, sodium thiosulfate, polyethylene glycol, and derivatives thereof; (3) a lipid-soluble adjusting agent such as 2,2?-thiodiethanol, propylene glycol, and derivatives thereof; and (4) a borate compound such as boric acid, tetraboric acid, disodium tetraborate, and derivatives thereof. The disclosed tissue clearing compositions are particularly suitable for use with non-neural, non-osseous tissues or organs.

Abstract: A semiconductor package structure includes an electronic device having an exposed region adjacent to a first surface, a dam surrounding the exposed region of the semiconductor die and disposed on the first surface, the dam having a top surface away from the first surface, an encapsulant encapsulating the first surface of the electronic device, exposing the exposed region of the electronic device. A surface of the dam is retracted from a top surface of the encapsulant. A method for manufacturing the semiconductor package structure is also provided.

Abstract: A close-end fuel cell and an anode bipolar plate thereof are provided. The anode bipolar plate includes an airtight conductive frame and a conductive porous substrate disposed within the airtight conductive frame. In the airtight conductive frame, an edge of a first side has a fuel inlet, and an edge of a second side has a fuel outlet. The conductive porous substrate has at least one flow channel, where a first end of the flow channel communicates with the fuel inlet, a second end of the flow channel communicates with the fuel outlet. The flow channel is provided with a blocking part near the fuel inlet to divide the flow channel into two areas.

Abstract: A flip-chip light-emitting diode structure capable of emitting trichromatic spectrum and a manufacturing method thereof, including a blue-green light layer with a light-stimulated green light-emitting structure and an electron-stimulated blue light-emitting structure, a bonding layer and a red light layer with a light-stimulated red light-emitting structure. The manufacturing method uses a sapphire bonding layer as the bonding layer, and forming the blue-green light layer and the red light layer by growing epitaxy on two sides of the sapphire bonding layer; or, after growing the blue-green light layer and the red light layer by epitaxy respectively, uses the bonding layer to connect.

Abstract: A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.

Abstract: A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper passive component pattern, and the second layer includes a lower passive component pattern, wherein the upper passive component pattern is opposite to the lower passive component pattern. The first interconnection layer includes at least one first interconnect structure electrically connected on the upper passive component pattern. The second interconnection layer includes at least one second interconnect structure electrically connected on the passive component pattern. The first interconnect structure on the upper passive component pattern is hybrid bonded with the second interconnect structure on the lower passive component pattern. Therefore, the upper passive component pattern and the lower passive component pattern are joined by hybrid bonding to form a passive device.