Abstract: A dual sensor imaging system and a calibration method thereof are provided. The dual sensor imaging system includes at least one color sensor, at least one infrared ray (IR) sensor, a storage device, and a processor. The processor is configured to load and execute a computer program stored in the storage device to: control the color sensor and the IR sensor to respectively capture multiple color images and multiple IR images of an imaging scene by adopting multiple capturing conditions; calculate multiple color image parameters of the color image captured under each capturing condition and multiple IR image parameters of the IR image captured under each capturing condition to be used to calculate a difference between a brightness of the color image and a brightness of the IR image; and determine an exposure setting suitable for the color sensor and the IR sensor according to the calculated difference.

Abstract: A floated-type shielding mechanism including a cover, a shielding sheet, and a flexible conductor is provided. The cover is adapted to be fixed to a circuit board and covers a plurality of input/output (IO) ports of the circuit board. The shielding sheet is movably disposed at the cover and a back plate, and has a plurality of openings respectively corresponding to the IO ports. The flexible conductor deformably protrudes from an inner surface of the shielding sheet and is adapted to contact the IO ports. When the circuit board, the back plate, and the floated-type shielding mechanism are assembled into a case, the IO ports are exposed from a case opening and the flexible conductor is adapted to be deformed by pressing so that the shielding sheet presses against an inner wall surface around the case opening.

Abstract: Examples of the present disclosure relate generally to a printing apparatus and, more particularly, to apparatuses, systems, and methods for printing utilizing laser print head and reactive media.

Abstract: A semiconductor device package and a method for manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a sensor module, a connector, and a stress buffer structure. The sensor module is disposed on the carrier. The connector is connected to the carrier. The stress buffer structure connects the connector to the sensor module.

Abstract: An air-cooling fuel cell stack includes fuel cells, wherein each of the fuel cells includes an anode bipolar plate, a cathode bipolar plate, a membrane electrode assembly (MEA) between the anode and cathode bipolar plates, and an anode sealing member. The MEA includes an anode side structure, a cathode side structure, and an ion conductive membrane (ICM), and the ICM is sandwiched between the anode side structure and the cathode side structure. The anode sealing member is disposed at a periphery of the anode side structure and sandwiched by the anode bipolar plate and the ICM. The anode sealing member includes a first sealing material and a second sealing material, a Shore hardness of the first sealing material is different from that of the second sealing material, and an arrangement direction of the first and second sealing materials is perpendicular to a compression direction of the plurality of fuel cells.

Abstract: A semiconductor structure in which the upper and lower semiconductor wafers are bonded by a hybrid bonding method is provided. The two semiconductor wafers each have discontinuous multiple metal traces or spiral coil-shaped metal traces. By hybrid bonding the two semiconductor wafers, multiple discontinuous metal traces are bonded together to form an inductance element with a continuous and non-intersecting path, or the two spiral coil-shaped metal traces are bonded together to form an inductance element. In this semiconductor structure, the inductance element formed by hybrid bonding has the advantage that the inductance value is easily adjusted.

Abstract: An optical module includes: a carrier; an optical element disposed on the upper side of the carrier; and a housing disposed on the upper side of the carrier, the housing defining an aperture exposing at least a portion of the optical element, an outer sidewall of the housing including at least one singulation portion disposed on the upper side of the carrier, wherein the singulation portion of the housing is a first portion of the housing, and wherein the housing further includes a second portion and a surface of the singulation portion of the housing is rougher than a surface of the second portion of the housing.

Abstract: A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper electrode pattern, and the second layer includes a lower electrode pattern, wherein the upper electrode pattern is opposite to the lower electrode pattern. The first interconnection layer includes a plurality of first interconnect structures electrically connected on the upper electrode pattern. The second interconnection layer includes a plurality of second interconnect structures electrically connected on the lower electrode pattern. The first interconnect structures on the upper electrode pattern are hybrid bonded with the second interconnect structures on the lower electrode pattern. Therefore, the upper electrode patterns and the lower electrode patterns are joined by hybrid bonding to form a capacitor element.

Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.

Abstract: A communications apparatus includes a plurality of communications circuits and a coexistence management circuit. Each communications circuit is configured to provide wireless communications services in compliance with a protocol. The coexistence management circuit is configured to manage radio activities of the communications circuits. In response to a detection result of at least two radio activities to occur in a subsequent packet time, the coexistence management circuit is configured to determine whether an interference signal related to said at least two radio activities falls in a predetermined frequency band, and when the interference signal falls in the predetermined frequency band, the coexistence management circuit is configured to adjust a transmission power or an execution time of one of said at least two radio activities.

Abstract: A semiconductor device package includes a carrier, a semiconductor device, a lid, a conductive post, a first patterned conductive layer, a conductive element disposed between the first conductive post and the first patterned conductive layer, and an adhesive layer disposed between the lid and the carrier. The conductive post is electrically connected to the first patterned conductive layer. The semiconductor device is electrically connected to the first patterned conductive layer. The lid is disposed on the carrier, and the lid includes a second patterned conductive layer electrically connected to the first conductive post.

Abstract: An optical package structure and a method for manufacturing an optical package structure are provided. The optical package structure includes a sensor, an optical component and a fixing element. The optical component directly contacts the sensor. An interfacial area is defined by a contacting region of the optical component and the sensor. The fixing element is disposed outside of the interfacial area for bonding the optical component and the sensor.

Abstract: A modular vehicle body includes a pair of outer frames. An inner board space with a fixed width is defined between the outer frames. Each outer frame includes a front side board and a door sill. The front side board includes a main board provided with a vertical board having a predetermined width. A first flange is provided on a side of the vertical board. The door sill includes an inner board provided with a horizontal board having a predetermined width. A second flange is provided on a side of the horizontal board. The inner board is fixedly coupled to the main board. The first flange and the second flange form an outer edge. A width between the outer edges of the pair of outer frames is set to correspond to a width of a vehicle body.

Abstract: A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper electrode pattern, and the second layer includes a lower electrode pattern, wherein the upper electrode pattern is opposite to the lower electrode pattern. The first interconnection layer includes a plurality of first interconnect structures electrically connected on the upper electrode pattern. The second interconnection layer includes a plurality of second interconnect structures electrically connected on the lower electrode pattern. The first interconnect structures on the upper electrode pattern are hybrid bonded with the second interconnect structures on the lower electrode pattern. Therefore, the upper electrode patterns and the lower electrode patterns are joined by hybrid bonding to form a capacitor element.

Abstract: In an embodiment, a method (of manufacturing fins for a semiconductor device) includes: forming a first layer (on a semiconductor substrate) that has first spacers and etch stop layer (ESL) portions which are interspersed; forming second spacers on central regions of the first spacers and the ESL portions; removing exposed regions of the first spacers and the ESL portions and corresponding underlying portions of the semiconductor substrate; removing the second spacers resulting in corresponding first capped semiconductor fins and second capped semiconductor fins that are organized into first and second sets; each member of the first set having a first cap with a first etch sensitivity; and each member of the second set having a second cap with a different second etch sensitivity; and eliminating selected ones of the first capped semiconductor fins and selected ones of the second capped semiconductor fins.

Abstract: A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.

Abstract: A semiconductor package structure includes an organic substrate having a first surface, a first recess depressed from the first surface, a first chip over the first surface and covering the first recess, thereby defining a first cavity enclosed by a back surface of the first chip and the first recess, and a second chip over the first chip. The first cavity is an air cavity or a vacuum cavity.

Abstract: A semiconductor device package includes a carrier, a die, an encapsulation layer and a thickness controlling component. The die is disposed on the carrier, wherein the die includes a first surface. The encapsulation layer is disposed on the carrier, and encapsulates a portion of the first surface of the die. The encapsulation layer defines a space exposing another portion of the first surface of the die. The thickness controlling component is disposed in the space.