Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device includes a gate to control the device, a drain coupled to the gate formed in a well of a first type, a source to form a current path with the drain, and a first field oxide region disposed between the gate and the drain. The gate is formed over a first portion of the well of the first type and a channel portion of the well of the second type. The LDMOS also includes a second field oxide region, which is disposed between the edges of the drain and the well of the second type. A dummy polysilicon layer, which is formed to cover approximately one half of the second field oxide with a remaining portion of the dummy polysilicon layer covering a second portion of the well of the second type, reduces the electric field in the drift region.

Abstract: A method includes forming a first rectangular mesa from a layer of semiconducting material and forming a first dielectric layer around the first mesa. The method further includes forming a first rectangular mask over a first portion of the first mesa leaving an exposed second portion of the first mesa and etching the exposed second portion of the first mesa to produce a reversed T-shaped fin from the first mesa.

Abstract: An improved pigment spacing composition and method of manufacture. A coating composition wherein the pigment particles are spaced more uniformly resulting in improved coating properties. In another embodiment, the present invention relates to a composition having nanoparticles interacting with pigmentary titanium dioxide to provide for more uniform spacing of the titanium dioxide.

Abstract: A method for forming fin structures for a semiconductor device that includes a substrate and a dielectric layer formed on the substrate is provided. The method includes etching the dielectric layer to form a first structure, depositing an amorphous silicon layer over the first structure, and etching the amorphous silicon layer to form second and third fin structures adjacent first and second side surfaces of the first structure. The second and third fin structures may include amorphous silicon material. The method further includes depositing a metal layer on upper surfaces of the second and third fin structures, performing a metal-induced crystallization operation to convert the amorphous silicon material of the second and third fin structures to a crystalline silicon material, and removing the first structure.

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.

Abstract: An acidic etcher solution for etching a substrate's surface. The acidic etcher solution includes an acid and a pH indicator, the pH indicator having at least one color transition at a pH below 7. The acidic etcher solution having an initial color at an initial pH when applied to the surface to allow determination of the evenness of the coating and the etcher having a second color at a second pH higher than the first pH wherein visual inspection allows for a determination that the etcher is substantially finished reacting.

Abstract: An improved pigment spacing composition and method of manufacture. A coating composition wherein the pigment particles are spaced more uniformly resulting in improved coating properties. In another embodiment, the present invention relates to a composition having nanoparticles interacting with pigmentary titanium dioxide to provide for more uniform spacing of the titanium dioxide.

Abstract: A near field antenna is disclosed which is configured to read an RFID label such that a localized electric E field emitted by the antenna at an operating wavelength resides substantially within a zone defined by the near field. The localized E field directs a current distribution along an effective length of the antenna corresponding to a half-wave to a full-wave structure.

Abstract: A circuit carrier is provided. The circuit carrier includes a substrate, a patterned circuit layer, and a solder mask layer. The patterned circuit layer is deposed on a surface of the substrate and has two passive component electrode pads. The solder mask layer covers the surface of the substrate, and includes a first solder mask opening, a second solder mask opening, and a third solder mask opening. The first solder mask opening and the second solder mask opening expose the passive component electrode pads respectively. The third solder mask opening along its length direction is divided into a central area and two extension areas. The central area is between the first and the second solder mask openings. The extension areas are extending from the central area along the length direction to two sides, respectively. The width of the central area is smaller than the width of one the extension areas.

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a CVD process.

Abstract: An integrated electronic article surveillance (EAS) and radiofrequency identification (RFID) marker is provided which a semiconductor device which may he coupled to an antenna for receiving and retransmitting energy and signals to the antenna. A current receiving front end section of the semiconductor device communicates with at least one other section of the device so more than one function can be implemented upon receiving and retransmitting energy and signals. A first switch is operatively coupled to the front end section such that the functions are entirely but reversibly disabled upon closure of the first switch thereby effecting a reversible EAS function. A second switch is operatively coupled to the front end section such that at least one of the functions is at least partially disabled upon closure of the second switch. RFID functions of the marker am retained upon EAS deactivation.

Abstract: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.

Abstract: A reader device for electronic article surveillance (EAS) is disclosed which includes an exciter; a transmitter, the transmitter operatively coupled to the exciter via a first signal gate; a transmitter antenna operatively coupled to the transmitter; a receiver antenna operatively coupled to a receiver front end; and a signal detector, the receiver front end operatively coupled to the signal detector via a second signal gate, wherein the exciter generates a burst of electromagnetic energy in a pulse or a continuous wave at an operating frequency of a radiofrequency identification (RFID) tag within a read range of the EAS reader such that the energy level of the burst generates a residual or ring-down signal from the RFID tag indicating the presence of the RFID tag without activating the RED functions of the tag. The ring-down signal is read by the EAS reader as an EAS function.

Abstract: The present invention discloses a method for constructing an object by stacking up functional features thereof. The present invention is also exemplified with a drawing die. Functional features and their main control parameters can be identified through functional analysis, functional decomposition and geometric analysis. In the present invention, a design knowledge base, a functional feature library, a functional feature module and a graphic user interface can be utilized optionally. Moreover, the present invention can be implemented on the Windows XP system through a commercial CAD software and an API.

Abstract: The present invention provides an improved micro combined connector structure, wherein a connector is structured to include a base, a cover, a movable cover and an earth strip. The base is provided with first and second containing recesses disposed therein, wherein the first containing recess enables electrical connecting to a SIM (Subscriber Identity Module) card, and the second containing recess enables electrical connecting to a memory card. A movable cover is fittingly disposed corresponding to position of the second containing recess of the base, and a protruding piece is located on the movable cover corresponding to the earth strip located on a side of the base. Closing of the movable cover enables the protruding piece and the earth strip to make contact and produce an electrical conduction, thereby enabling the movable cover to form an earthing state to achieve the objective of preventing interference and reducing noise.

Abstract: A conduction structure for infrared microbolometer sensors and a method for sensing electromagnetic radiation may be provided. The microbolometer may include a first conductor layer and a second conductor layer. The microbolometer further may include a bolometer layer between the first conductor layer and the second conductor layer.

Abstract: The present invention provides an improved micro combined connector structure, wherein a connector is structured to include a base, a cover, a movable cover and an earth strip. The base is provided with first and second containing recesses disposed therein, wherein the first containing recess enables electrical connecting to a SIM (Subscriber Identity Module) card, and the second containing recess enables electrical connecting to a memory card. A movable cover is fittingly disposed corresponding to position of the second containing recess of the base, and a protruding piece is located on the movable cover corresponding to the earth strip located on a side of the base. Closing of the movable cover enables the protruding piece and the earth strip to make contact and produce an electrical conduction, thereby enabling the movable cover to form an earthing state to achieve the objective of preventing interference and reducing noise.

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Abstract: An electronic flame analog installation for incense wax canister providing better light-emitting results, compact structure among members, simple construction and powerful utility includes a lampshade containing an electronic light emitting installation; and a lamp holder disposed to the lower end of the lampshade to accommodate the tip of the lampshade to adapt to the tip of the incense wax canister; the lamp holder and the top of the canister being effectively fixed and connected to each other; and the built in electronic light-emitting installation produces electronic flame to provide the canister better flame imitation results.

Abstract: Methods are provided for fabricating a semiconductor device having an impurity doped region in a silicon substrate. The method comprises forming a metal silicide layer electrically contacting the impurity doped region and depositing a conductive layer overlying and electrically contacting the metal silicide layer. A dielectric layer is deposited overlying the conductive layer and an opening is etched through the dielectric layer to expose a portion of the conductive layer. A conductive material is selectively deposited to fill the opening and to electrically contact the impurity doped region.