Patents by Inventor Ming Tung

Ming Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8445380
    Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a method for forming a via structure includes forming a via in a semiconductor substrate, wherein via sidewalls of the via are defined by the semiconductor substrate; forming a dielectric layer on the via sidewalls; removing the dielectric layer from a portion of the via sidewalls; and forming a conductive layer to fill the via, wherein the conductive layer is disposed over the dielectric layer and the portion of the via sidewalls. In an example, the dielectric layer is an oxide layer.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: May 21, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Chih Hsieh, Richard Chu, Ming-Tung Wu, Martin Liu, Lan-Lin Chao, Chia-Shiung Tsai
  • Publication number: 20130056825
    Abstract: A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 7, 2013
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chien-Chung Chen, Ming-Tung Lee, Shih-Chin Lien, Shyi-Yuan Wu
  • Publication number: 20130037914
    Abstract: A bipolar junction transistor and a manufacturing method for the same are provided. The bipolar junction transistor includes a well region, an emitter electrode, a base electrode, a collector electrode, and a conductive layer. The emitter electrode, the base electrode and the collector electrode are separated from each other by the well region. The conductive layer is on the well region between the base electrode and the collector electrode.
    Type: Application
    Filed: August 8, 2011
    Publication date: February 14, 2013
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chin-Wei Chang, Ching-Lin Chan, Chin-Shien Lu, Ming-Tung Lee, Shuo-Lun Tu
  • Publication number: 20130037891
    Abstract: The present disclosure provides a method including providing a first substrate; and forming a microelectromechanical system (MEMS) device on a first surface of the first substrate. A bond pad is formed on at least one bonding site on the first surface of the first substrate. The bonding site is recessed from the first surface. Thus, a top surface of the bond pad may lie below the plane of the top surface of the substrate. A device with recessed connective element(s) (e.g., bond pad) is also described. In further embodiments, a protective layer is formed on the recessed connective element during dicing of a substrate.
    Type: Application
    Filed: August 9, 2011
    Publication date: February 14, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")
    Inventors: Hsin-Ting Huang, Jung-Huei Peng, Shang-Ying Tsai, Yao-Te Huang, Ming-Tung Wu, Ping-Yin Liu, Xin-Hua Huang, Yuan-Chih Hsieh
  • Patent number: 8357547
    Abstract: A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: January 22, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Ming-Tung Lee, Shih-Chin Lien, Chia-Huan Chang
  • Patent number: 8354716
    Abstract: A semiconductor device for use in a relatively high voltage application that comprises a substrate, a first n-type well region in the substrate to serve as a high voltage n-well (HVNW) for the semiconductor device, a pair of second n-type well regions in the first n-type well region, a p-type region in the first n-type well region between the second n-type well regions, a pair of conductive regions on the substrate between the second n-type well regions, and a number of n-type regions to serve as n-type buried layers (NBLs) for the semiconductor device, wherein the NBLs are located below the first n-type region and dispersed in the substrate.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: January 15, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsueh I Huang, Ming-Tung Lee, Shyi-Yuan Wu
  • Publication number: 20120270350
    Abstract: A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 25, 2012
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ming-Tung Lee, Shih-Chin Lien, Chia-Huan Chang
  • Publication number: 20120240855
    Abstract: The deposition apparatus has a plurality of said transmission mechanisms arranged therein in a symmetrical manner. Each transmission mechanism comprises: a drive shaft, formed with a tapered end; a driving wheel, configured with a shaft hole for the tapered end to bore coaxially therethrough; a plurality of slide pieces, radially mounted to the driving wheel; a first elastic member, mounted enabling the plural slide pieces to be ensheathed thereby; a second elastic member, disposed between the first elastic member and the first axial end of the drive shaft while being mounted to the periphery of the driving wheel; an enclosure, configured with an opening; wherein, the driving wheel that is moving in a reciprocating manner drives the sliding pieces to slide in radial directions, thereby, causing the outer diameter of the first elastic member to change accordingly and enabling the opening of the enclosure to open or close in consequence.
    Type: Application
    Filed: July 6, 2011
    Publication date: September 27, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chen-Chung Du, Ming-Tung Chiang, Muh-Wang Liang, Kuan-Chou Chen, Tean-Mu Shen, Jung-Chen Ho
  • Publication number: 20120238091
    Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a method for forming a via structure includes forming a via in a semiconductor substrate, wherein via sidewalls of the via are defined by the semiconductor substrate; forming a dielectric layer on the via sidewalls; removing the dielectric layer from a portion of the via sidewalls; and forming a conductive layer to fill the via, wherein the conductive layer is disposed over the dielectric layer and the portion of the via sidewalls. In an example, the dielectric layer is an oxide layer.
    Type: Application
    Filed: May 25, 2012
    Publication date: September 20, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Chih Hsieh, Richard Chu, Ming-Tung Wu, Martin Liu, Lan-Lin Chao, Chia-Shiung Tsai
  • Publication number: 20120235300
    Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.
    Type: Application
    Filed: May 25, 2012
    Publication date: September 20, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Chih Hsieh, Richard Chu, Ming-Tung Wu, Martin Liu, Lan-Lin Chao, Chia-Shiung Tsai
  • Publication number: 20120233513
    Abstract: In a method for creating a clock domain in a layout of an integrated circuit, a test circuit of the integrated circuit includes a plurality of first scan cells and a plurality of second scan cells, the first scan cells are arranged to be on a first scan chain, and the second scan cells are arranged to be on a second scan chain. The method includes: for a first region in the layout, determining whether the first region needs a test clock domain adjustment according to densities of first scan cells and second scan cells within the first region; and when it is determined that the first region needs the test clock domain adjustment, arranging at least one first scan cell within the first region to be on the second scan chain.
    Type: Application
    Filed: August 19, 2011
    Publication date: September 13, 2012
    Inventors: Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Jen-Yang Wen, Chien-Mo Li
  • Patent number: 8227877
    Abstract: A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: July 24, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Ming-Tung Lee, Shih-Chin Lien, Chia-Huan Chang
  • Patent number: 8207595
    Abstract: A semiconductor device includes a substrate wafer, a dielectric layer overlying the substrate wafer, a patterned conductor layer in the dielectric layer, and a first barrier layer overlying the conductor layer. A silicon top wafer is bonded to the dielectric layer. A via is formed through the top wafer and a portion of the dielectric layer to the first barrier layer. A sidewall dielectric layer is formed along inner walls of the via, adjacent the top wafer to a distance below an upper surface of the top wafer, forming a sidewall dielectric layer shoulder. A sidewall barrier layer is formed inward of the sidewall dielectric layer, lining the via from the first barrier layer to the upper surface of the top wafer. A conductive layer fills the via and a top barrier layer is formed on the conductive layer, the sidewall barrier layer, and the top wafer.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: June 26, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Chih Hsieh, Richard Chu, Ming-Tung Wu, Martin Liu, Lan-Lin Chao, Chia-Shiung Tsai
  • Publication number: 20120149152
    Abstract: The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a bonding pad on a first substrate; forming wiring pads on the first substrate; forming a protection material layer on the first substrate, on sidewalls and top surfaces of the wiring pads, and on sidewalls of the bonding pad, such that a top surface of the bonding pad is at least partially exposed; bonding the first substrate to a second substrate through the bonding pad; opening the second substrate to expose the wiring pads; and removing the protection material layer.
    Type: Application
    Filed: December 13, 2010
    Publication date: June 14, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Ying Tsai, Jung-Huei Peng, Hsin-Ting Huang, Hung-Hua Lin, Ming-Tung Wu, Ping-Yin Liu, Yao-Te Huang, Yuan-Chih Hsieh
  • Publication number: 20120121807
    Abstract: The present invention provides a film deposition system and method by combining a plurality of gas supplying apparatuses and a deposition apparatus being in communication with the plurality of gas supplying apparatuses. By means of respectively providing different types of vapor precursors with high concentration and high capacity into a process chamber of the deposition apparatus through the plurality of gas supplying apparatus, the deposition reaction is accelerated so as to improve the efficiency of film deposition. In an embodiment of the gas supplying apparatus, it utilizes a first gas for providing high pressure toward on a liquid surface of the precursor, thereby transporting the precursor into an atomizing and heating unit whereby the precursor is atomized and then is heated so as to form a high-concentration and high capacity vapor precursor transported by another carrier gas.
    Type: Application
    Filed: January 21, 2011
    Publication date: May 17, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ming-Tung Chiang, Shih-Chin Lin
  • Publication number: 20120080761
    Abstract: A semiconductor device includes a substrate wafer, a dielectric layer overlying the substrate wafer, a patterned conductor layer in the dielectric layer, and a first barrier layer overlying the conductor layer. A silicon top wafer is bonded to the dielectric layer. A via is formed through the top wafer and a portion of the dielectric layer to the first barrier layer. A sidewall dielectric layer is formed along inner walls of the via, adjacent the top wafer to a distance below an upper surface of the top wafer, forming a sidewall dielectric layer shoulder. A sidewall barrier layer is formed inward of the sidewall dielectric layer, lining the via from the first barrier layer to the upper surface of the top wafer. A conductive layer fills the via and a top barrier layer is formed on the conductive layer, the sidewall barrier layer, and the top wafer.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 5, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Chih Hsieh, Richard Chu, Ming-Tung Wu, Martin Liu, Lan-Lin Chao, Chia-Shiung Tsai
  • Publication number: 20120038839
    Abstract: A micro projector module according to the present invention is provided. The micro projector module includes a substrate, a controller chip, a LCOS chip, a glass and a liquid crystal layer. The controller chip is positioned on the upper surface of the substrate and electrically connected to the substrate. The LCOS chip is positioned on the controller chip and electrically connected to the substrate. The glass is positioned on the LCOS chip and the liquid crystal layer is disposed between the LCOS chip and glass.
    Type: Application
    Filed: October 7, 2010
    Publication date: February 16, 2012
    Applicant: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITED
    Inventors: Yueh Ming TUNG, Chia Ming YANG, Shu Hui LIN, Yuan Wei LIU, Wei Fang LIN
  • Publication number: 20120037989
    Abstract: LDMOS devices having a single-strip contact pad in the source region, and related methods of manufacturing are disclosed. The LDMOS may comprise a first well lightly doped with a first dopant and formed into a portion of a substrate, the first well having a drain region at its surface heavily doped with the first dopant, and a second well lightly doped with a second dopant formed in another portion of the substrate, the second well having a source region at its surface comprising first portions heavily doped with the first dopant directly adjacent second portions heavily doped with the second dopant. Also, the LDMOS device may comprise a field oxide at the upper surface of the substrate between the source and drain regions, and contacting the first well but separated from the second well, and a gate formed partially over the field oxide and partially over the source region.
    Type: Application
    Filed: August 16, 2010
    Publication date: February 16, 2012
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hsueh-I Huang, Shuo-Lun Tu, Ming-Tung Lee, Yin-Fu Huang, Shih-Chin Lien, Shyi-Yuan WU
  • Publication number: 20120012900
    Abstract: A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening.
    Type: Application
    Filed: July 14, 2010
    Publication date: January 19, 2012
    Inventors: Ming-Tung LEE, Shih-Chin LIEN, Chia-Huan CHANG
  • Publication number: 20120012841
    Abstract: A through-silicon via (TSV) testing structure is disclosed herein and includes a plurality of controllers, a plurality of transmitters and a plurality of receivers. The controllers are configured to output a first controlling signal and a second controlling signal. The transmitters are respectively connected to the output end of the through-silicon via and one of the controllers, and output a testing output signal in accordance with the first controlling signal and the second controlling signal. The receivers are respectively connected to the input end of the through-silicon via and another one of the controllers, and input a testing input signal in accordance with the first controlling signal and the second controlling signal.
    Type: Application
    Filed: February 23, 2011
    Publication date: January 19, 2012
    Applicant: Global Unichip Corporation
    Inventors: Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng