Abstract: A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.

Abstract: Kits and methods that combine whitening/stain removal of teeth with remineralization are disclosed. These kits advantageously comprise separate compositions comprising a soluble calcium salt, a soluble orthophosphate salt, and a soluble peroxide, in order to optimize the stability of these components for storage and/or the activity of these components upon use. The active ingredients may also be separated in a solid composition (e.g., a powder) or in a stable dispersion comprising a non-aqueous dispersion medium.

Abstract: Disclosed is a centering device of a spindle motor. The centering device includes a body portion which is disposed on the rotor of the spindle motor, and which is provided with a central hole for accommodating the shaft of the spindle motor; and a plurality of centering elastic finger units, located along the periphery of the body portion. Each centering elastic finger unit includes at least two elastic fingers. Each elastic finger includes a free end which extends from the body portion in the circumferential direction of the rotor, and which has a contact portion adapted to urge against an optical disk to guide the centering of the optical disk with respect to the shaft of the spindle motor. Preferably, the contact portion is formed into an arc surface so as to reduce the contact area and thus the friction between the elastic fingers and the disk.

Abstract: A biodegradable plastic composition is provided. The biodegradable plastic composition includes a starch in a range from about 25% to about 50% by weight of the composition, a synthetic biodegradable resin in a range from about 10% to about 40% by weight of the composition, a synthetic resin with linear alkenes in a range from about 5% to about 15% by weight of the composition, an affinity agent in a range from about 8% to about 20% by weight of the composition, a coupling agent in a range from about 1% to about 3% by weight of the composition, and an additives in a range from about 1% to about 15% by weight of the composition. Further, a producing method of the biodegradable plastic also is provided.

Abstract: Calcium peroxyphosphate compounds and dental compositions comprising these compounds that combine both whitening/stain removal of teeth with remineralization are disclosed. The calcium peroxyphosphate compounds are capable of releasing, in an aqueous environment, whitening and remineralization effective amounts of calcium ion, phosphate ion, and active oxygen. Preferred compounds are calcium peroxymonophosphate or calcium diperoxymonophosphate compounds. These compounds may be used in humans and other animals, including other mammals.

Abstract: A semiconductor device has a lower metal layer, a lower dielectric layer on top of the lower metal layer, an upper metal layer on top of the lower dielectric layer, an upper dielectric layer on top of the upper metal layer, and a contact region formed as a cavity that extends through the upper dielectric layer, the upper metal layer and the lower dielectric layer for access to a solder pad portion of the lower metal layer. A dielectric lining layer lines a peripheral cavity-confining surface of the cavity, and is transverse to a plane of the lower metal layer. The dielectric lining layer isolates the upper metal layer from the lower metal layer while permitting access to the solder pad portion of the lower metal layer. An electrical contact fills the cavity, and enables external electrical connection with the lower metal layer.

Abstract: A method for fabricating a non-volatile memory is provided. A stacked structure including a tunneling layer, a trapping layer, a barrier layer, and a control gate is formed on a substrate. A source region and a drain region are formed beside the stacked structure in the substrate. A silicon oxide spacer is formed on the sidewalls of the stacked structure. An ultraviolet-resistant lining layer is formed on the surfaces of the substrate and the stacked structure to prevent the ultraviolet light from penetrating into the trapping layer. A dielectric layer is formed on the ultraviolet-resistant lining layer. A contact being electrically connected to the control gate is formed in the dielectric layer. A conducting line electrically connected to the contact is formed on the dielectric layer. A lost-surface-charge lining layer is formed on the surfaces of the dielectric layer and the conducting line to reduce the antenna effect.

Abstract: A method and apparatus for time-division demultiplexing and decompressing a compressed input stimulus 421, provided at a selected data-rate R1 421, into a decompressed stimulus 424, 426, 433, 435, driven at a selected data-rate R2 442, for driving selected scan chains in a scan-based integrated circuit 401. The scan-based integrated circuit 401 contains a high-speed clock CK1 443, a low-speed clock CK2 442, and a plurality of scan chains 411, . . . , 418, each scan chain comprising multiple scan cells coupled in series. The method and apparatus comprises using a plurality of time-division demultiplexors (TDDMs) 402, 403 and time-division multiplexors (TDMs) 408, 409 for shifting stimuli 421 and test responses 444 in and out of high-speed I/O pads. When applied to the scan-based integrated circuit 401 embedded with one or more pairs of decompressors 404, 405 and compressors 406, 407, it can further reduce the circuit's test time, test cost, and scan pin count.

Abstract: Disclosed is a centering device of a spindle motor. The centering device includes a body portion which is disposed on the rotor of the spindle motor, and which is provided with a central hole for accommodating the shaft of the spindle motor; and a plurality of centering elastic finger units, located along the periphery of the body portion. Each centering elastic finger unit includes at least two elastic fingers. Each elastic finger includes a free end which extends from the body portion in the circumferential direction of the rotor, and which has a contact portion adapted to urge against an optical disk to guide the centering of the optical disk with respect to the shaft of the spindle motor. Preferably, the contact portion is formed into an arc surface so as to reduce the contact area and thus the friction between the elastic fingers and the disk.

Abstract: A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.

Abstract: A telephone line connection and disconnection circuit has a diode bridge coupled to the telephone line which converts different voltages of the telephone line into a voltage referenced to ground. A switching circuit is coupled to the diode bridge which opens and closes a conductive pathway for connecting and disconnecting a telephony product from the telephone line. A resistive element is coupled to the diode bridge and the switching circuit which allows for the conductive pathway to be normally closed. An optical isolator is coupled to the switching circuit and the resistive element for sending a control signal to the circuit when required.

Abstract: A semiconductor chip module includes a chip-mounting member having opposite first and second surfaces, a set of circuit traces, and a plurality of plated through holes that extend through the first and second surfaces and that are connected to the circuit traces. A dielectric tape member bonds adhesively a semiconductor chip on the chip-mounting member. A first conductor unit connects electrically contact pads on a pad mounting surface of the semiconductor chip and the circuit traces. A plurality of solder balls are disposed on one of the first and second surfaces of the chip-mounting member, are aligned with and are connected to the plated through holes in the chip-mounting member, respectively.

Abstract: A semiconductor chip module includes a chip-mounting member having opposite first and second surfaces, a set of circuit traces, and a plurality of plated through holes that extend through the first and second surfaces and that are connected to the circuit traces. A dielectric tape member bonds adhesively a semiconductor chip on the chip-mounting member. A first conductor unit connects electrically contact pads on a pad mounting surface of the semiconductor chip and the circuit traces. A plurality of solder balls are disposed on one of the first and second surfaces of the chip-mounting member, are aligned with and are connected to the plated through holes in the chip-mounting member, respectively.

Abstract: A hermetically sealed electrical switch assembly comprises a casing having an opening end. A cover is sealingly attached to said opening end of said casing for forming a primary volume hermetically sealed from external environment. Received in said primary volume are a switch means and a magnetic responsive means. A magnetic activating means is fitted at the upper surface of said cover for effecting the movement of said magnetic responsive means. The switch means comprises electrical contacts to change the conducting state of a power circuit with which said switch means is connected, a switching lever which can change its positions according to the conducting state of the power circuit. The magnetic responsive means couples with said switching lever for moving with it.

Abstract: An electronic component base for an electronic component is disclosed to have a top wall adapted to accommodate an electronic component core, diagonally extended wire grooves in the top wall for guiding out lead wires of the loaded electronic component core, a bottom wall, a plurality of electrically conducting zones in the bottom wall, four peripheral walls, four chamfered angles alternatively connected between the peripheral walls, and four conducting side grooves respectively extended from the wire grooves to the electrically conducting zones for receiving the lead wires of the electronic component core from the wire grooves.

Abstract: A fixture for assembling an inductor is a flat locating seat with an upper side thereof having a locating nest corresponding to the RI core of the inductor and having a central part corresponding to a locating part disposed at the bottom of the DR core in the inductor. The inductor can be located at the fixture and operations such as soldering and spot gluing can be performed steadily.

Abstract: A semiconductor chip module includes first and second semiconductor chips, and a dielectric tape layer. The first semiconductor chip has a pad mounting surface with a plurality of first bonding pads provided thereon. The dielectric tape layer has opposite first and second adhesive surfaces. The first adhesive surface is adhered onto the pad mounting surface of the first semiconductor chip. The dielectric tape layer is formed with a plurality of holes at positions registered with the first bonding pads to expose the first bonding pads. Each of the holes is confined by a wall that cooperates with a registered one of the first bonding pads to form a contact receiving space. A plurality of conductive contacts are placed in the contact receiving spaces, respectively. The second semiconductor chip has a chip mounting surface adhered onto the second adhesive surface of the dielectric tape layer.

Abstract: A semiconductor device has a lower metal layer, a lower dielectric layer on top of the lower metal layer, an upper metal layer on top of the lower dielectric layer, an upper dielectric layer on top of the upper metal layer, and a contact region formed as a cavity that extends through the upper dielectric layer, the upper metal layer and the lower dielectric layer for access to a solder pad portion of the lower metal layer. A dielectric lining layer lines a peripheral cavity-confining surface of the cavity, and is transverse to a plane of the lower metal layer. The dielectric lining layer isolates the upper metal layer from the lower metal layer while permitting access to the solder pad portion of the lower metal layer. An electrical contact fills the cavity, and enables external electrical connection with the lower metal layer.

Abstract: A multi-chip semiconductor module includes first and second substrates. The first substrate has opposite first and second surfaces, a plurality of first conductive vias that extend through the first and second surfaces, and a first circuit layout patterned on the second surface and connected electrically to the first conductive vias. The second substrate has opposite first and second surfaces, a plurality of second conductive vias that extend through the first and second surfaces of the second substrate, a second circuit layout patterned on the second surface of the second substrate and connected electrically to the second conductive vias, and a chip-receiving opening formed therein. The first surface of the second substrate is bonded on the second surface of the first substrate such that the second circuit layout is connected electrically to the first circuit layout through the first and second conductive vias.

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a first conductive bump on a substrate, forming a second conductive bump on a semiconductor chip, forming a plurality of spaced apart dielectric supporting pads on one of the substrate and the semiconductor chip, mounting the semiconductor chip on the substrate to confine therebetween a gap, bonding together the first and second conductive bumps, and forming an insulating layer that fills in the gap and that encapsulates the supporting pads and the first and second conductive bumps.