Abstract: A fire extinguisher includes a container having a chamber for receiving a dry chemical agent, a cover attached to the container and having a passage for allowing the dry chemical agent to flow out of the cover, and an agitating device received in the container for agitating the dry chemical agent and for preventing the dry extinguishing agent from being hardened. A rod is rotatably received in the container and extended out of the container and includes an agitator, and a hand wheel is secured to the rod for rotating the rod and the agitator relative to the container. A carrier is rotatably attached to a seat for supporting the container and for adjustably securing the container to the seat at selected angular positions.

Abstract: A stack chip package structure and a manufacturing method thereof are disclosed. The method comprises: providing a first substrate; disposing a first chip on the first substrate; disposing a second chip and at least one second substrate on the first chip, wherein the second substrate is electrically connected to the first chip; bonding at least one first connecting wire connected between the second chip and the second substrate; bonding at least one second connecting wire connected between the first substrate and the second substrate; and forming a package body on the first substrate to encapsulate the first chip, the second chip, the second substrate, the first connecting wire and the second connecting wire.

Abstract: A memory card with electrostatic discharge (ESD) protection and a manufacturing method thereof are provided. The memory card includes a circuit board, a set of contacts, at least one chip and an ESD protection path. The signal paths of the board is not exposed at the edge of the circuit board. The ESD protection path for transmitting ESD current is disposed on the circuit board. Furthermore, a part of the ESD protection path extends to the edge of the circuit board.

Abstract: A method and apparatus time-division demultiplexes and decompresses a compressed input stimulus provided at a selected data rate R1, into a decompressed stimulus, driven at a selected data rate R2, for driving selected scan chains in a scan-based integrated circuit using a plurality of time-division demultiplexors and time-division multiplexors for shifting stimuli and test responses in and out of high-speed I/O pads in order to reduce test time, test cost, and scan pin count. A synthesis method is also proposed for synthesizing the time-division multiplexors, decompressors, compressors, and time-division multiplexors.

Abstract: A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.

Abstract: An integrated heat dissipating assembly includes two heat sinks, a heat dissipating fan mounted between the two sinks and a body provided below the two heat sinks and the heat dissipating fan. The body is composed of a hollow body, a pump received inside the hollow body and a base attached to a bottom face of the hollow body for conducting heat from a heat source. The hollow body is divided into receiving spaces respectively communicating with water channels of the two heat sinks such that cooling water flowing inside the hollow body and the water channels of the two heat sinks is able to take away heat from the base. The heat is then dissipated by cool air due to the heat dissipating fan.

Abstract: A heat dissipator fastening kit includes two retaining bars, at least one and as many as three different brackets and multiple fasteners. The retaining bars are resilient, attach to opposite sides of an appropriate heat dissipator and respectively have two ends. The bracket attaches to a motherboard around a CPU and to the retaining bars and has several embodiments to accommodate different types of CPUs, e.g. AM2, K8, LGA775 or P4, and their motherboards. The fasteners attach the retaining bars to a heat dissipator and the bracket and the bracket to a motherboard. With such an arrangement, the heat dissipator fastening kit will be convenient and easy to use.

Abstract: A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.

Abstract: A film includes a removable base material, a resin layer and a plurality of arc elastomers. The resin layer is a partially-cured resin which is in a half-melting state with viscosity at a temperature higher than a first temperature and in a solid state without viscosity at a temperature lower than a second temperature, and the resin layer in a solid state is adhered on the base material. The arc elastomers are disposed inside the resin layer. The present invention further provides a chip packaging process using the film.

Abstract: An integrated heat dissipating assembly includes two heat sinks, a heat dissipating fan mounted between the two sinks and a body provided below the two heat sinks and the heat dissipating fan. The body is composed of a hollow body, a pump received inside the hollow body and a base attached to a bottom face of the hollow body for conducting heat from a heat source. The hollow body is divided into receiving spaces respectively communicating with water channels of the two heat sinks such that cooling water flowing inside the hollow body and the water channels of the two heat sinks is able to take away heat from the base. The heat is then dissipated by cool air due to the heat dissipating fan.

Abstract: The present invention provides a hollow cathode discharging apparatus including a hollow anode electrode, a hollow cathode electrode insulatedly fixed in the hollow anode electrode, a gas distribution pipe fixed in the hollow cathode electrode. The hollow anode electrode and the hollow cathode electrode are formed with anode openings and cathode openings respectively. Defined by the gas distribution pipe and the hollow cathode electrode and along the axis thereof is a spiral pathway winding through the cathode openings, so as to form a plurality of continuous and communicated reaction chambers. The gas distribution pipe is disposed with gas separation apertures communicated and adapted to introduce a reactive gas into the reaction chambers. The communicated reaction chambers enable uniform distribution of the reactive gas and thereby facilitate scale-up of the apparatus in axial. Accordingly, the present invention overcomes drawbacks of the prior art.

Abstract: A memory card with electrostatic discharge (ESD) protection is provided. The memory card includes a board, a set of contacts, at least one chip and an ESD protection path. The board having a signal path not electrically connected to the edge of the board. The ESD protection path for transmitting ESD current is disposed on the board. Furthermore, a part of the ESD protection path extends to the edge of the board.

Abstract: A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.

Abstract: A semiconductor package structure is disclosed. The structure includes a lead frame, a semiconductor chip, a plurality of metallic conducting wires, an encapsulation, a barrier layer and a pure tin layer, herein the lead frame has at least one die pad, a plurality of inner leads and outer leads. The semiconductor chip is disposed on the die pad. The metallic conducting wires electrically connect the semiconductor chip and the inner leads. The encapsulation packages of the semiconductor chip, the die pad, the metallic conducting wires and the inner leads. The barrier layer covers each of the outer leads to prevent an inter-metallic compound produced by the outer leads and pure tin. The pure tin layer covers the barrier layer to increase the solder wettability for the outer leads. Besides, a method for manufacturing the semiconductor package structure is disclosed.

Abstract: A prepreg for fuel cell obtained by soaking reinforcing glass fiber cloth in resin mixture and having the soaked cloth pre-dried to form incompletely cured prepreg which can be press-cured under temperature range of 60?˜200? to provide good mechanical and electrical property and high bonding strength, and when applied to fuel cell for bonding together the parts and components of the fuel cell the prepreg can also provide the effect of preventing crossover of fuel of the fuel cell and helping to the normal operation of the fuel cell.

Abstract: A wafer stage includes a bottom insulator plate secured on a bottom portion of the processing chamber; a central pedestal plate mounted on the bottom insulator plate; and a removable top insulator cover having a chamber fittingly accommodating the central pedestal plate and the bottom insulator plate, wherein the top insulator cover has a flat top surface on which a wafer is placed.

Abstract: A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.

Abstract: A board for water sport gears includes an elongate body and a shock absorbing device is attached on a top surface of the board. The device includes a plurality of ribs and a plurality of walls are connected between the first ribs so as to define a plurality of chambers between the ribs and the walls. An upper layer and a bottom layer are respectively connected to two opposite sides of the device. The ribs and the walls are made by resilient material so that it can be deformed to absorb shocks. The device can also be connected between inner and outer layers of bags to protect the contents in the bags.