Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

Abstract: A motor drive unit for driving a motor of a motorized window treatment may comprise software-based and hardware-based implementations of a process for detecting and resolving a stall condition in the motor, where the hardware-based implementation is configured to reduce power delivered to the motor if the software-based implementation has not first reduced the power to the motor. A control circuit may detect a stall condition of the motor, and reduce the power delivered to the motor after a first period of time from first detecting the stall condition. The motor drive unit may comprise a stall prevention circuit configured to reduce the power delivered to the motor after a second period of time (e.g., longer than the first period of time) from determining that a rotational sensing circuit is not generating a sensor signal while the control circuit is generating a drive signal to rotate the motor.

Abstract: This invention relates to a method of treating Attention-Deficit Hyperactivity Disorder by orally administering to a subject a composition containing a Radix Polygalae (Polygala tenuifolia Willd) extract (such as PDC-1421). A solid dosage form of the composition can be prepared into the gelatin capsule. The oral administration of the composition in healthy volunteers was safe and well-tolerated for the daily dose from 380 mg to 3800 mg. The composition can be administered chronically over at least 25 days; the daily dose is administered once per day, twice per day, or three times per day, wherein each dose is 380-760 mg of the botanical extract.

Abstract: The present invention discloses a SAADC circuit having optimized linearity. A lower-bit capacitor array includes lower-bit capacitors. A higher-bit capacitor array includes unit capacitors. In an initializing mode, a control circuit sorts the unit capacitors according to unit capacitances thereof such that the unit capacitors are configured to be higher-bit capacitors having a linearity parameter within a predetermined range. In an operation mode, the capacitor array receives an analog input signal and a reference voltage to generate an analog output signal, a comparator generates a comparison result according to the analog output signal and the control circuit generates an enabling signal according to the comparison result based on the successive approximation mechanism to selectively enable the higher-bit and the lower-bit capacitors to connect to the reference voltage by using the capacitor enabling circuit and outputs a digital output signal according to the final comparison result.

Abstract: A method for manufacturing an ultra-thin glass substrate includes: providing a glass base material preset with n substrate areas and a skeleton area surrounding the substrate areas; at least forming an etching protection layer on an upper surface and a lower surface of each substrate area of the glass base material, respectively; at least etching the skeleton area of the glass base material to separate the substrate areas from the glass base material, and form a stress dissipation edge along an edge of each substrate area; and removing the etching protection layer to get independent glass substrates. A method for manufacturing a display panel is also disclosed. An aim is to prevent quality of the ultra-thin glass substrate from damage caused by scribing wheel cutting or laser cutting, therefore the quality of the ultra-thin glass substrate is improved.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed on the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a dielectric layer having a first portion and a second portion, wherein the first portion of the dielectric layer is formed on a portion of the gate structure, and the second portion of the dielectric layer is formed on the substrate and extending to a portion of the drain region, wherein the dielectric layer includes at least one recess on the second portion. An associated fabricating method is also disclosed.

Abstract: A method for manufacturing ultra-thin glass substrates and a method for manufacturing a display panel are provided, including: providing a glass base material preset with n substrate areas and a skeleton area surrounding the substrate areas, wherein n is greater than or equal to 1; at least forming an etching protection layer, wherein, each etching protection layer includes a main area and at least one thinned area extending along a preset bending path; at least etching the skeleton area of the glass base material to separate the substrate areas from the glass base material, forming at least one bending stress dissipation groove, and forming a stress dissipation edge along an edge of each substrate area; removing the etching protection layer to get independent glass substrates having the bending stress dissipation groove. The method improves bending performance along the preset bending path.

Abstract: Some implementations described herein provide techniques and apparatuses for polishing a perimeter region of a semiconductor substrate so that a roll-off profile at or near the perimeter region of the semiconductor substrate satisfies a threshold. The described implementations include depositing a first layer of a first oxide material across the semiconductor substrate followed by depositing a second layer of a second oxide material over the first layer of the first oxide material and around a perimeter region of the semiconductor substrate. The described implementations further include polishing the second layer of the second oxide material over the perimeter region using a chemical mechanical planarization tool including one or more ring-shaped polishing pads oriented vertically over the perimeter region.

Abstract: A semiconductor device is provided. The semiconductor device comprises an output circuit configured to be electrically connected between a driving circuit and an external load circuit, and a protection circuit electrically connected to the output circuit and the driving circuit. The protection circuit comprises a first transistor having a base electrode, a collector electrode and an emitter electrode and a second transistor having a base electrode, a collector electrode and an emitter electrode. The base electrode of the first transistor is electrically connected to the collector electrode of the second transistor.

Abstract: A semiconductor die includes a semiconductor substrate and a transistor array disposed over the semiconductor substrate. The transistor array includes unit cells and spacers. The unit cells are disposed along rows of the transistor array extending in a first direction and columns of the transistor array extending in a second direction perpendicular to the first direction. The spacers encircle the unit cells. The unit cells include source contacts and drain contacts separated by interlayer dielectric material portions. First sections of the spacers contacting the interlayer dielectric material portions are thicker than second sections of the spacers contacting the source contacts and the drain contacts.

Abstract: A method of manufacturing a semiconductor device includes disposing a plurality of a first type of light sensing units on a substrate; and disposing a plurality of a second type of light sensing units arranged on the substrate. Each of the first type of light sensing units is operable to receive less radiation than each of the second type of light sensing units. At least one of the second type of light sensing units is adjacent to a portion of at least one of the first type of light sensing units. The method includes disposing a first isolation structure between one of the first type of light sensing units and one of the second type of light sensing units; and disposing a second isolation structure between the adjacent first type of light sensing units. The method includes disposing a reflective layer above the first type of light sensing units.

Abstract: The present disclosure provides an integrated circuit (IC) structure with a solar cell and an image sensor array. An integrated structure according to the present disclosure includes a first substrate including a plurality of photodiodes, an interconnect structure disposed on the first substrate, a first bonding layer disposed on the interconnect structure, a second bonding layer disposed on the first bonding layer, a second substrate disposed on the second bonding layer, and a transparent conductive oxide layer disposed on the second substrate.

Abstract: A lock of the present invention includes a housing, a rotating hook, a driving apparatus, and a lock body. An end of the housing includes a front-end opening. The front-end opening faces a same direction as an extending direction of an X-axis, and deviates from a center of a section parallel to a Y-Z plane of the end of the housing that includes the front-end opening, where the X-axis, a Y-axis, and a Z-axis are orthogonal. The rotating hook is arranged in the housing and is rotatable relative to the housing, and includes a front end and a rear end, where the front end at least partially extends out of the front-end opening, and the rear end extends in an opposite direction to the front end. The driving apparatus is arranged in the housing and is movable to change an opening width of the front end. The lock body is arranged in the housing, and when the lock body is locked, the lock body restricts movement of the driving apparatus.

Abstract: A pixel sensor may include a vertically arranged (or vertically stacked) photodiode region and floating diffusion region. The vertical arrangement permits the photodiode region to occupy a larger area of a pixel sensor of a given size relative to a horizontal arrangement, which increases the area in which the photodiode region can collect photons. This increases performance of the pixel sensor and permits the overall size of the pixel sensor to be reduced. Moreover, the transfer gate may surround at least a portion of the floating diffusion region and the photodiode region, which provides a larger gate switching area relative to a horizontal arrangement. The increased gate switching area may provide greater control over the transfer of the photocurrent and/or may reduce switching delay for the pixel sensor.

Abstract: A device and methods of forming the same are described. The device includes a substrate and a first bipolar junction transistor (BJT) disposed over the substrate. The first BJT includes a first base region, a first emitter region, and a first collector region. The device further includes a second BJT disposed over the substrate adjacent the first BJT, and the second BJT includes a second base region, a second emitter region, and a second collector region. The device further includes an interconnect structure disposed over the first and second BJTs, and the interconnect structure includes a first conductive line electrically connected to the first emitter region and the second base region and a second conductive line electrically connected to the first collector region and the second collector region.

Abstract: A method for determining a reference signal sequence, a terminal device, and a network device, the including receiving, by a terminal device, first indication information sent by a network device, determining, by the terminal device, a target resource based on the first indication information, determining, by the terminal device, a reference signal sequence based on parameters of a first bandwidth and parameters of a second bandwidth, and sending or receiving, by the terminal device, the reference signal sequence on the target resource.

Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

Abstract: A method for manufacturing ultra-thin glass substrates and a method for manufacturing a display panel are provided. The method for manufacturing ultra-thin glass substrates includes: providing a glass base material preset with n substrate areas and a skeleton area surrounding the substrate areas; at least forming an etching protection layer on each substrate area of the glass base material; immersing the glass base material in a reaction chamber having etching medium; after the edge of each substrate area is etched to form the stress dissipation edge and the substrate areas are separated from the glass base material, the substrate areas falling down by gravity and falling into the basket; pulling the basket out of the reaction chamber to get the substrate areas separated from the glass base material; removing the etching protection layer to get independent glass substrates.