Abstract: A semiconductor arrangement includes a photodiode extending to a first depth from a first side in a substrate. An isolation structure laterally surrounds the photodiode and includes a first well that extends into a first side of the substrate. A deep trench isolation extends into a second side of the substrate and at least a portion of the deep trench isolation underlies the first well.

Abstract: A semiconductor arrangement includes a photodiode extending to a first depth from a first side in a substrate. An isolation structure laterally surrounds the photodiode and includes a first well that extends into a first side of the substrate. A deep trench isolation extends into a second side of the substrate and at least a portion of the deep trench isolation underlies the first well.

Abstract: In a color display, a color filter layer includes a dielectric layer with an array of photonic crystals, an electroluminescent material disposed on the color filter layer, and electrodes arranged to electrically energize the electroluminescent material to output white light. Each photonic crystal includes a two-dimensional (2D) array of features. The 2D array of features includes a central cavity within which the features of the 2D array of features are omitted. Each photonic crystal is tuned to a resonant wavelength by a periodicity of the two-dimensional array of features. The array of photonic crystals may include, for example, red, green, and blue photonic crystals arranged to form an array of pixels spanning a display area of the color display, in which each pixel includes at least one red photonic crystal, at least one green photonic crystal, and at least one blue photonic crystal.

Abstract: A pixel sensor includes a transfer fin field effect transistor (finFET) to transfer a photocurrent from a photodiode to a drain region. The transfer finFET includes at least a portion of the photodiode, an extension region associated with the drain region, a plurality of channel fins, and a transfer gate at least partially surrounding the channel fins to control the operation of the transfer finFET. In the transfer finFET, the transfer gate is wrapped around (e.g., at least three sides) of each of the channel fins, which provides a greater surface area over which the transfer gate is enabled to control the transfer of electrons. The greater surface area results in greater control over operation of the finFET, which may reduce switching times of the pixel sensor (which enables faster pixel sensor performance) and may reduce leakage current of the pixel sensor relative to a planar transfer transistor.

Abstract: A pixel sensor may include a deep trench isolation (DTI) structure that extends the full height of a substrate in which a photodiode of the pixel sensor is included. Incident light entering the pixel sensor at a non-orthogonal angle is absorbed or reflected by the DTI structure along the full height of the substrate. In this way, the DTI structure may reduce, minimize, and/or prevent the incident light from traveling through the pixel sensor and into an adjacent pixel sensor along the full height of the substrate. This may increase the spatial resolution of an image sensor in which the DTI structure is included, may increase the overall sensitivity of the image sensor, may reduce and/or prevent color mixing between pixel sensors of the image sensor, and/or may decrease image noise after color correction.

Abstract: In various embodiments methods and devices are provided for the detection and/or quantification of an analyte. In certain embodiments a device is provided comprising an aqueous two-phase system (ATPS) comprising a mixed phase solution that separates into a first phase solution and a second phase where, in use, said first phase solution becomes a leading phase and said second phase solution becomes a lagging phase; a lateral-flow assay (LFA); and a probe and/or a development reagent, where in use, said probe associates with said first phase solution in said leading phase of said ATPS and/or said development reagent associates with said second phase solution in said lagging phase of said ATPS. In certain embodiments a “one-pot” system of purifying and amplifying a nucleic acid is provided utilizing, e.g., an ATPS and isothermal amplification reagents.

Abstract: A parameter analysis method and a parameter analysis system for metal additive manufacturing are provided. The parameter analysis method includes: establishing a powder bed model; simulating a multi-track melting result of the powder bed model according to a plurality of laser parameters to generate a melting model; analyzing the melting model to calculate a plurality of position divergences of a plurality of melting powders of the melting model, and defining a plurality of melting surface powders according to the position divergences; analyzing the melting surface powders to calculate a surface average curvature of the melting model; and determining a laser hatch in the laser parameters allows metal additive manufacturing to meet a quality as needed according to whether the surface average curvature is between a first curvature threshold and a second curvature threshold, the first curvature threshold being smaller than the second curvature threshold.

Abstract: In a color display, a color filter layer includes a dielectric layer with an array of photonic crystals, an electroluminescent material disposed on the color filter layer, and electrodes arranged to electrically energize the electroluminescent material to output white light. Each photonic crystal includes a two-dimensional (2D) array of features. The 2D array of features includes a central cavity within which the features of the 2D array of features are omitted. Each photonic crystal is tuned to a resonant wavelength by a periodicity of the two-dimensional array of features. The array of photonic crystals may include, for example, red, green, and blue photonic crystals arranged to form an array of pixels spanning a display area of the color display, in which each pixel includes at least one red photonic crystal, at least one green photonic crystal, and at least one blue photonic crystal.

Abstract: In some embodiments, the present disclosure relates to a method that includes bonding a first wafer to a second wafer to form a wafer stack and removing a top portion of the second wafer. A first trim blade having a first blade width is aligned over the second wafer. The first trim blade is used to form a trench that separates a central portion of the second wafer from a peripheral portion of the second wafer. The trench is arranged at a first distance from an outer perimeter of the second wafer, and extends from a top surface of the second wafer to a trench depth beneath the top surface of the first wafer. A second trim blade having a second blade width is aligned over the peripheral portion, the second blade width being greater than the first blade width. The peripheral portion is removed using the second trim blade.

Abstract: In a color display, a color filter layer includes a dielectric layer with an array of photonic crystals, an electroluminescent material disposed on the color filter layer, and electrodes arranged to electrically energize the electroluminescent material to output white light. Each photonic crystal includes a two-dimensional (2D) array of features. The 2D array of features includes a central cavity within which the features of the 2D array of features are omitted. Each photonic crystal is tuned to a resonant wavelength by a periodicity of the two-dimensional array of features. The array of photonic crystals may include, for example, red, green, and blue photonic crystals arranged to form an array of pixels spanning a display area of the color display, in which each pixel includes at least one red photonic crystal, at least one green photonic crystal, and at least one blue photonic crystal.

Abstract: A pixel array may include a group of time-of-flight (ToF) sensors. The pixel array may include an image sensor comprising a group of pixel sensors. The image sensor may be arranged among the group of ToF sensors such that the image sensor is adjacent to each ToF sensor in the group of ToF sensors.

Abstract: An integrated circuit device includes a dielectric structure within a metal interconnect over a substrate. The dielectric structure includes a cavity. A first dielectric layer provides a roof for the cavity. A second dielectric layer provides a floor for the cavity. A material distinct from the first dielectric layer and the second dielectric layer provides a side edge for the cavity. In a central area of the cavity, the cavity has a constant height. The height may be selected to provide a low parasitic capacitance between features above and below the cavity. The roof of the cavity may be flat. A gate dielectric may be formed over the roof. The dielectric structure is particularly useful for reducing parasitic capacitances when employing back-end-of-line (BEOL) transistors.

Abstract: Some implementations described herein provide pixel sensor configurations and methods of forming the same. In some implementations, one or more transistors of a pixel sensor are included on a circuitry die (e.g., an application specific integrated circuit (ASIC) die or another type of circuitry die) of an image sensor device. The one or more transistors may include a source follower transistor, a row select transistor, and/or another transistor that is used to control the operation of the pixel sensor. Including the one or more transistors of the pixel sensor (and other pixel sensors of the image sensor device) on the circuitry die reduces the area occupied by transistors in the pixel sensor on the sensor die. This enables the area for photon collection in the pixel sensor to be increased.

Abstract: The invention relates to the field of powder coatings, and specifically discloses a heat-curable powder coating composition and a preparation method thereof. The powder coating composition comprises: i) component A comprising at least one amorphous solid polyester resin compound having a Michael donor reactive group; ii) component B comprising at least one amorphous ethylenically unsaturated solid polyester resin with a Michael acceptor reactive group; iii) component C comprising at least one (semi) crystalline solid reactive diluent; iv) component D comprising at least one epoxy group-containing solid substance; v) component E comprising at least one basic catalyst. The present invention also discloses a preparation method of the above heat-curable powder coating composition. By adopting the invention, ultra-low temperature curing can be realized. The curing temperature is as low as 90-110° C., and the curing time is short.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory cell. In some embodiments, a memory film is deposited over a substrate and comprises a bottom electrode layer, a top electrode layer, and a data storage film between the top and bottom electrode layers. A hard mask film is deposited over the memory film and comprises a conductive hard mask layer. The top electrode layer and the hard mask film are patterned to respectively form a top electrode and a hard mask over the top electrode. A trimming process is performed to decrease a sidewall angle between a sidewall of the hard mask and a bottom surface of the hard mask. An etch is performed into the data storage film with the hard mask in place after the trimming process to form a data storage structure underlying the top electrode.

Abstract: The present invention provides a multi-phase structured UV-curable powder coating resin and a preparation method thereof, comprising (1) obtaining an emulsion of a liquid UV resin by heating the liquid UV resin and an emulsifier, dispersing, and adding deionized water for emulsification; (2) melting and dispersing a solid UV resin, a phase change agent, an emulsifier, and deionized water; adding the emulsion of the liquid UV resin with stirring to thoroughly mix; temperature is lowered during the stirring to obtain a suspension; (3) press filtering the suspension of the UV-curable powder coating resin to obtain a filter cake; (4) drying and classifying the filter cake to obtain the multi-phase structured UV-curable powder coating resin. The multi-phase structured UV-curable powder coating resin is prepared from the aforementioned method. The present disclosure has the properties of both the liquid and solid UV resin and can be sprayed as a powder coating.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes bonding a first semiconductor wafer to a second semiconductor wafer. A bond interface is disposed between the first and second semiconductor wafers. The first semiconductor wafer has a peripheral region laterally surrounding a central region. A support structure is formed between a first outer edge of the first semiconductor wafer and a second outer edge of the second semiconductor wafer. The support structure is disposed within the peripheral region. A thinning process is performed on the second semiconductor wafer.

Abstract: A dual purpose camera is provided. The dual purpose camera has a doccam mode and a webcam mode. The dual purpose camera includes a base, a supporting member, and a camera. The supporting member is detachably or rotatably coupled to the base. The camera is rotatably or detachably coupled to the supporting member. The camera rotates with respect to a reference plane of the dual purpose camera between a first position and a second position. When it is detected that the camera is attached to the base and the camera rotates from the first position to the second position, the camera automatically outputs a 180 degree rotated image.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. A first conductive structure overlies a substrate. A second conductive structure overlies the first conductive structure. A data storage structure is disposed between the first and second conductive structures. The data storage structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. Respective bandgaps of the first, second, and third dielectric layers are different from one another.

Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.