Abstract: A method for removing a chromide coating from the surface of a substrate is described. The coating is treated with a composition which includes an acid having the formula HxAF6, where “A” can be Si, Ge, Ti, Zr, Al, or Ga; and x is 1–6. An exemplary acid is hexafluorosilicic acid. The composition may also include a second acid, such as phosphoric acid or nitric acid. In some instances, a third acid is employed, such as hydrochloric acid. A related repair method for replacing a worn or damaged chromide coating is described. The coating is often applied to portions of turbine engine components made from superalloy materials.

Abstract: Data reading can be easily and precisely performed by setting specific conditions in writing into a selected memory cell. A memory cell has a structure, in which an interelectrode material layer is sandwiched between a first electrode and a second electrode. Data is stored by a change in a resistance value between the first electrode and the second electrode. The resistance value when a memory element is in a high resistance state is expressed as R_mem_high; the resistance value when the memory element is in a low resistance state is expressed as R_mem_low1; the resistance value of a load circuit is expressed as R_load; the reading voltage is expressed as Vread by setting the voltage of a second power supply line to the reference voltage; and the threshold voltage is expressed as Vth_critical. In writing data into the memory cell, the low resistance state is created so that these parameters satisfy specific relations.

Abstract: A storage device includes a first electrode, a second electrode facing the first electrode, an inter-electrode material layer provided between the first electrode and the second electrode, and a voltage application unit applying a predetermined voltage to the first and the second electrodes. Furthermore, an oxidation-reduction active material changeable into an electrode reaction inhibition layer by applying voltages to the first and the second electrodes is contained in a region that is covered by an electric field, the electric field being generated when the voltage is applied, and the electrode reaction inhibition layer is either formed along an interface region between the second electrode and the inter-electrode material layer, or changes an area thereof, or disappears depending on an application condition of the voltage to the first and the second.

Abstract: A method for removing a chromide coating from the surface of a substrate is described. The coating is treated with a composition which includes an acid having the formula HxAF6, where “A” can be Si, Ge, Ti, Zr, Al, or Ga; and x is 1-6. An exemplary acid is hexafluorosilicic acid. The composition may also include a second acid, such as phosphoric acid or nitric acid. In some instances, a third acid is employed, such as hydrochloric acid. A related repair method for replacing a worn or damaged chromide coating is described. The coating is often applied to portions of turbine engine components made from superalloy materials.

Abstract: A storage device comprises a memory element and an applying means for applying a voltage to the memory element wherein the memory element changes its characteristic to record thereon information with application of a voltage to the memory element by the applying means, the memory element further changing its characteristic when the same information is recorded on the memory element continuously. The memory element has a recording method which comprises the steps of detecting content of information that has already been recorded on the memory element when the information is recorded, comparing the information that has already been recorded on the memory element with information to be recorded on the memory element, applying a voltage to the memory element to make an ordinary information recording process if the two information are different from each other and disabling the ordinary information recording process when the two information are identical to each other.

Abstract: The present invention concerns an ingress noise control system and an ingress noise blocking device which are used in a cable system to suppress ingress noise. In the cable system providing two-way communication using different frequency bands for transmission of upstream and downstream signals, the ingress noise control system includes, within a distribution unit, a two-way amplification unit, etc. provided in an upstream signal transmission path, a synchronous detection controller 6 for synchronously detecting the upstream signal transmitted from terminal equipment and separated by a low-pass filter 4 in a second separation filter 2, a gate switch circuit 5 which is turned on by the synchronous detection controller 6 to pass the upstream signal only when the upstream signal is synchronously detected, and an indicator 7 for indicating the on/off state of the gate switch circuit 5.

Abstract: A storage device is provided. The storage device includes a number of storage cells arranged and each having a storage element and an active element including a MOS transistor that controls access to the storage element, and in which applying a voltage to the storage element the resistance value of the storage element changes and information is recorded wherein the resistance value of a storage element after information has been written is prevented from becoming lower than necessary and in which information writing can be easily performed.

Abstract: A memory device able to be produced without requiring high precision alignment, a method of production of the same, and a method of use of a memory device produced in this way, wherein a peripheral circuit portion (first semiconductor portion) formed by a first minimum processing dimension is formed on a substrate, a memory portion (second semiconductor portion) formed by a second minimum processing dimension smaller than the first minimum processing dimension is stacked above it, and the memory portion (second semiconductor portion) is stacked with respect to the peripheral circuit portion (first semiconductor portion) with an alignment precision rougher than the second minimum processing dimension or wherein memory cells configured by 2-terminal devices are formed in regions where word lines and bit lines intersect in the memory portion, and contact portions connecting the word lines and bit lines and the peripheral circuit portions are arranged in at least two columns in directions in which the word lines

Abstract: A semiconductor memory device provided with a plurality of memory cells each including first transistors having first conductivity type and second transistors having a second conductivity type, each memory cell comprising a first active region where channels of the first transistors are formed and a second active region where channels of the second transistors are formed, the first and second active regions being arranged so that the directions of channel currents of the transistors become parallel to each other in each cell and being separated between adjoining memory cells in a direction perpendicular to the directions of channel current.

Abstract: A semiconductor memory device provided with a plurality of memory cells each including first transistors having first conductivity type and second transistors having a second conductivity type, each memory cell comprising a first active region where channels of the first transistors are formed and a second active region where channels of the second transistors are formed, the first and second active regions being arranged so that the directions of channel currents of the transistors become parallel to each other in each cell and being separated between adjoining memory cells in a direction perpendicular to the directions of channel current.

Abstract: Provided are a semiconductor memory device and a method of manufacturing the same, in which landing pad layers in correspondence to contacts connecting to a power supply voltage line and a bit line can be easily formed in the same layer as node wiring, thereby simplifying the manufacturing process. Resist patterns having a roughly C shape i.e., patterns of two sets of node wiring are formed not in the same direction in all memory cells but in a different direction from each other between neighboring cells in up-down and right-left directions. Furthermore, out of four sides of each memory cell resist patterns i.e., patterns of the landing pad layer are formed on the two sides opposite the two sides close to the resist patterns for the two sets of node wiring. Accordingly, the landing pad layers can be formed in the same layer as the node wiring, the landing pad layers corresponding to contacts connecting to a grounded line, power supply voltage line and bit line in the upper layer from the node wiring.

Abstract: A semiconductor memory device which can suppress the occurrence of corner rounding through the resist patterning process to achieve a reduction in cell size and higher integration. A relationship between a channel width DT.W of the drive transistor, a channel length DT.L of the drive transistor, a channel width WT.W of the word transistor and a channel length WT.L of the word transistor is given by: (DT.W/WT.W)/(WT.L/DT.L)<1.2. The channel width DT.W of the drive transistor is equal to the channel width WT.W of the word transistor, to reduce steps in the patterns of p-type active regions. The channel length WT.L of the word transistor is larger than the channel length DT.L of the drive transistor, that is, (WT.L/DT.L)>1.

Abstract: Provided is a semiconductor memory device in which SRAM has a construction such that an nMOS transistor formation region and a pMOS transistor formation region are disposed in a direction along which a bit line extends, thereby reducing delay in the bit line caused by wiring parasitic capacity. A main word line has a shape such that the main word line is disposed every two memory cell rows avoiding a bit line contact and part of the main word line extends to the row adjacent to the two rows. Accordingly, the main word line can be easily formed in the layer below the bit lines. In the bit lines, wiring parasitic capacity between the main word line and the bit line is reduced and therefore delay in the bit line is eliminated. As a result, time delay in memory operation is reduced.

Abstract: A semiconductor memory device provided with a plurality of memory cells each including first transistors having first conductivity type and second transistors having a second conductivity type, each memory cell comprising a first active region where channels of the first transistors are formed and a second active region where channels of the second transistors are formed, the first and second active regions being arranged so that the directions of channel currents of the transistors become parallel to each other in each cell and being separated between adjoining memory cells in a direction perpendicular to the directions of channel current.

Abstract: A user of a station or the like acquires a right to use a rental box installed in or around the station, and key information to open the box is recorded in a key information recording medium. The purchased goods are stored in the box which the user has a right to use. The user sets the key information recording medium in the rental box when he/she arrives at a station. The box open/close controlling device extracts the key information of the box from the box user information recording device, and checks it with the key information read out from the key information recording medium and judges whether the-box is opened or not. In this situation, the box status that the box status monitoring device detected is referred to, if required. In addition, information necessary for the users, such as presence of the goods in the box, a result of the checking of the key information, or the like is displayed in the display device.

Abstract: A split word type static RAM 1 with TFT load elements has improved resistance to soft errors and has more reliable wiring for a bit line. In this static RAM 1, the structures for patterns for first and second driver transistors 17 and 18, and the structures for patterns for first and second word transistors 15 and 16 are respectively arranged symmetrically about a central point 0, and the structures for patterns for first and second TFTs 19 and 20 are arranged asymmetrically. The channel region 31 of the first TFT 19 is made long, on one part of which a capacitor is formed. A bit contact extends upwardly over a word transistor and is connected with a bit line.

Abstract: A semiconductor memory device provided with a plurality of memory cells each including first transistors having first conductivity type and second transistors having a second conductivity type, each memory cell comprising a first active region where channels of the first transistors are formed and a second active region where channels of the second transistors are formed, the first and second active regions being arranged so that the directions of channel currents of the transistors become parallel to each other in each cell and being separated between adjoining memory cells in a direction perpendicular to the directions of channel current.

Abstract: A semiconductor memory device enabling a reduction in size of a memory cell and higher integration. A drive transistor and a word transistor are formed in a p-type active region. Similarly, another drive transistor and another word transistor are formed in another p-type active region. A word line is wired so as to be substantially orthogonal to both of the p-type active regions. A pMOS load transistor is formed in an n-type active region, and another load transistor is formed in another n-type active region. A channel width of the drive transistor is greater than a channel width of the load transistor. Thereby, a cell area can be reduced while achieving the cell current and the SNM equivalent to those of a conventional SRAM cell.

Abstract: A semiconductor memory device which can reduce the size of a memory cell and increase the packing density is disclosed. Each memory cell comprises a p-type active region, an n-type active region, two word lines, a common gate line and a common gate line. Two memory cells are deviated by, for example, an amount of a half bit in the direction which perpendicularly crosses the word line direction. The memory cells are arranged with one of their parts overlapped with one another in the word line direction. Thus, the size of the memory cell can be reduced in the word line direction.

Abstract: A static random access memory device (SRAM) keeping a resistance value of a resistance element at a predetermined level regardless a process variation, by improving a special margin of a diffusion layer region at which the resistance element is formed and a node for connecting a gate electrode thereto. In the SRAM, there is provided a diffusion layer region in a substrate, having a first part of which may form a the resistance element, a second part of which is connected to the drain or source of the MIS access transistor, and a third part of which is connected to the source or drain of the MIS driver transistor and is defined the node, and there is provided an electrode layer connecting the gate of the MIS driver transistor and the node in the diffusion layer region.