Abstract: A cable for high speed data communications is provided. The cable includes a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer. The first inner conductor is substantially parallel to the second inner conductor and to a longitudinal axis. The cable includes a conductive shield wrapped around the first and second inner conductors, with an overlap of the conductive shield along and about the longitudinal axis. The overlap is aligned with a low current plane. The low current plane is substantially parallel to the first and second inner conductors, substantially equidistant from the first and second inner conductors, and substantially orthogonal to a plane including the first and second inner conductors.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to technical support management and provide a novel and non-obvious method, system and computer program product for intelligent problem tracking to optimize technical support. In an embodiment of the invention, a method for intelligent problem tracking can include receiving recorded information of tracked end user behavior collected in an end user computing system while the end user addresses a problem in the end user computing system, determining a level of technical sophistication of the user based upon the recorded information, selecting a technical support level corresponding to the determined level of technical sophistication of the user, and transmitting a resolution to the problem in a message to the end user computing system commensurate with the selected technical support level.

Abstract: In a particular embodiment, a method of manufacturing a printed circuit board (‘PCB’) with reduced dielectric loss includes fabricating conductive traces disposed upon layers of dielectric material; and fabricating the layers of dielectric material, including core layers and prepreg layers, with one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB. In the particular embodiment, the conductive traces are disposed upon layers of the dielectric material orthogonally with respect to one another and the pockets of air are aligned at an angle of 45 degrees with respect to the conductive traces.

Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of manufacturing a PCB. Embodiments include depositing upon layers of laminate printed circuit traces and joining the layers of laminate. Embodiments also include drilling at least one via hole through the layers of laminate and placing in the via hole a via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a second metal having a conductivity lower than the conductivity of copper.

Abstract: The present invention is directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a method including capacitively coupling a plating stub to ground so that the resonant frequency caused by the plating stub in a semiconductor package is shifted away from an operational frequency.

Abstract: Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.

Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.

Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of manufacturing a PCB. Embodiments include depositing upon layers of laminate printed circuit traces and joining the layers of laminate. Embodiments also include drilling at least one via hole through the layers of laminate and placing in the via hole a via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a second metal having a conductivity lower than the conductivity of copper.

Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.

Abstract: Techniques for optimizing a Business Process Model (BPM) having at least one work process are presented. At a simulation client, a determination is made whether a simulated business outcome associated with a test BPM satisfies a business value deficiency associated with a current BPM. In response to a determination that the simulated business outcome does not satisfy the business value deficiency, the test BPM is optimized. Once the simulation client determines that the simulated business outcome satisfies the business value deficiency, the test BPM is implemented as an actual BPM. Moreover, an actual business outcome associated with the actual BPM is generated. A determination is made whether the actual business outcome satisfies the simulated business outcome. In response to a determination that the actual business outcome does not satisfy the simulated business outcome, the actual BPM is optimized.

Abstract: Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations.

Abstract: A statistical approach can be used to efficiently supply an initial population that provides a good global description of a design space. The SI based simulation can then find a global best design within a reduced number of simulations. The statistical approach can be utilized to determine a plurality of potential best and worst case designs from a design space. The plurality of potential best and worst case designs from the design space seed or prime a SI based simulation. The best case designs are based on design parameters than can be controlled. The worst case designs are based on design parameters than cannot be controlled due. SI based simulations can then be run on the best case designs with respect to the worst case designs to determine probability of failure of the best case design.

Abstract: A device and method are disclosed wherein a receiver signal line within an integrated circuit may be selected for probing. In one embodiment, a plurality of signal pads and a test pad are provided on an external surface of an integrated circuit chip. A plurality of signal lines extends through the integrated circuit chip to the signal pads. A multiplexer on the integrated circuit chip is configured for individually selecting any of the signal lines. An amplifier on the integrated circuit chip amplifies a selected signal and communicates the amplified signal to an externally-accessible test pad to be probed.

Abstract: Dynamically managing power consumption of a computer, the computer including two or more graphics adapters, the computer having a number of graphics adapter configurations including one or more of the graphics adapters, where managing power consumption includes: monitoring, by a graphics driver, operation of a current graphics adapter configuration, the operation characterized by a graphics processing load; determining, in dependence upon the graphics processing load, whether operation of the current graphics adapter configuration conforms to predefined graphics processing criteria; if operation conforms, processing graphics, by the graphics adapter, for display with the one or more graphics adapters of the current graphics adapter configuration; and if operation does not conform, processing graphics, by the graphics adapter, for display with the one or more graphics adapters of another graphics adapter configuration.

Abstract: A method for electrical design space exploration includes receiving a template for an electrical design. Design component parameters associated with at least one component in the electrical design are also received. Weighted factors are assigned to design complexity parameters of the electrical design. The parameters of the complexity can include at least one of following: whether the electrical design is known, a number of the design component parameters, a level of interaction among the design component parameters, a time constraint and a memory restriction of a simulation, and whether a statistical analysis or a worst case approach is used to analyze an output of the simulation. A simulation approach for design space exploration of the electrical design is selected based on the weighted factors for the parameters of the complexity of the electrical design. The simulation is performed based on the selected simulation approach.

Abstract: Methods, apparatuses, and computer program products are disclosed for controlling plating stub reflections in a chip package. In one embodiment, a resonance optimizer determines performance characteristics of a bond wire that connects a chip to a substrate of a semiconductor chip mount. In this embodiment, the resonance optimizer selects, based on the performance characteristics of the bond wire, a line width for an open-ended plating stub that extends from a signal interconnect of the substrate to a periphery of the substrate, The resonance optimizer also generates a design of signal traces for the substrate, where the signal traces include the open-ended plating stub with the selected line width.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to via structure utilization in a PCB design and provide a novel and non-obvious method, system and computer program product for impedance discontinuity remediation for via stubs and connectors in a PCB. In one embodiment a method for impedance discontinuity remediation in a PCB can be provided. The method can include configuring a pre-distortion filter to negate an impedance discontinuity in an electrical signal caused by a transmission line with one of a via stub or a connector. The method further can include pre-distortion filtering an electrical signal before transmitting the electrical signal over the transmission line. Finally, the method can include transmitting the pre-distortion filtered electrical signal over the transmission line.

Abstract: A printed circuit board (‘PCB’) with reduced dielectric loss, including conductive traces disposed upon layers of dielectric material, the layers of dielectric material including core layers and prepreg layers, one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to via structure utilization in a PCB design and provide a novel and non-obvious method, system and computer program product for impedance discontinuity remediation for via stubs and connectors in a PCB. In one embodiment a method for impedance discontinuity remediation in a PCB can be provided. The method can include configuring a pre-distortion filter to negate an impedance discontinuity in an electrical signal caused by a transmission line with one of a via stub or a connector. The method further can include pre-distortion filtering an electrical signal before transmitting the electrical signal over the transmission line. Finally, the method can include transmitting the pre-distortion filtered electrical signal over the transmission line.

Abstract: Identifying an optimized test bit pattern for analyzing electrical communications channel topologies, including: ranking according to channel quality, from worst to best, a set of channel topologies for an electrical communications channel; and for each ranked channel topology beginning with the worst, carrying out the following steps in an iterative loop until a concatenated test bit pattern and a previously optimized test bit pattern are functionally equally fit: concatenating to a previously optimized test bit pattern an additional test bit pattern; optimizing the concatenated test bit pattern values for a next ranked channel in the subset, leaving the optimized values of the previously optimized test bit pattern unchanged; and comparing through use of a fitness function the relative qualities of the previously optimized test bit pattern and the optimized concatenated test bit pattern.