Abstract: A printed circuit board (‘PCB’) with reduced dielectric loss, including conductive traces disposed upon layers of dielectric material, the layers of dielectric material including core layers and prepreg layers, one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB.

Abstract: A method for electrical design space exploration includes receiving a template for an electrical design. Design component parameters associated with at least one component in the electrical design are also received. Weighted factors are assigned to design complexity parameters of the electrical design. The parameters of the complexity can include at least one of following: whether the electrical design is known, a number of the design component parameters, a level of interaction among the design component parameters, a time constraint and a memory restriction of a simulation, and whether a statistical analysis or a worst case approach is used to analyze an output of the simulation. A simulation approach for design space exploration of the electrical design is selected based on the weighted factors for the parameters of the complexity of the electrical design. The simulation is performed based on the selected simulation approach.

Abstract: Measuring control signal timing for synchronous dynamic random access memory (‘SDRAM’), including combining into a trigger signal for an oscilloscope display control signals of an SDRAM under test, the control signals derived only from a single type of memory operations; and driving, continually during both READ and WRITE operations to and from the SDRAM under test, the oscilloscope display with a memory bus data signal (‘DQ’) and a memory bus clock signal (‘DQS’) from the SDRAM under test.

Abstract: Embodiments of the invention are directed to transmission cables, and particularly to twinax cables, for transmitting digital data and other information between components in a data processing environment. One embodiment of the invention is directed to an information transmission cable that comprises first and second signal carrying conductors of specified length, each of the signal carrying conductors being disposed to carry information signals and having a longitudinal axis. The embodiment further includes an insulating structure comprising an amount of specified dielectric insulation material, the insulating structure being positioned to surround the first and second signal carrying conductors along their respective lengths, and acting to maintain the first and second signal conductors in spaced apart parallel relationship with each other.

Abstract: A computer implemented method, apparatus, and computer program product for managing organizational resources. The process combines social group data with management information data to form social network data, wherein social group data is derived from interactions among a plurality of users of a social group. The process analyzes the social network data to identify associations among the plurality of users, and generates a multidimensional social network model using the associations among the plurality of users. Thereafter, the process presents a set of recommendations for allocation of the organizational resources, wherein the set of recommendations are derived from the social network model.

Abstract: Cables and methods of manufacturing cables for high speed data communications, the cable including: a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer, the inner conductors and the dielectric layers parallel with and along a longitudinal axis; and folded conductive shield material wrapped in a rotational direction along and about the longitudinal axis around the inner conductors and the dielectric layers, including overlapped wraps along and about the longitudinal axis, the conductive shield material comprising a first conductive layer and second conductive layer separated by an inner-shield dielectric layer.

Abstract: A statistical approach can be used to efficiently supply an initial population that provides a good global description of a design space. The SI based simulation can then find a global best design within a reduced number of simulations. The statistical approach can be utilized to determine a plurality of potential best and worst case designs from a design space. The plurality of potential best and worst case designs from the design space seed or prime a SI based simulation. The best case designs are based on design parameters than can be controlled. The worst case designs are based on design parameters than cannot be controlled due. SI based simulations can then be run on the best case designs with respect to the worst case designs to determine probability of failure of the best case design.

Abstract: A device and method are disclosed wherein a receiver signal line within an integrated circuit may be selected for probing. In one embodiment, a plurality of signal pads and a test pad are provided on an external surface of an integrated circuit chip. A plurality of signal lines extends through the integrated circuit chip to the signal pads. A multiplexer on the integrated circuit chip is configured for individually selecting any of the signal lines. An amplifier on the integrated circuit chip amplifies a selected signal and communicates the amplified signal to an externally-accessible test pad to be probed.

Abstract: One embodiment provides a method of locating a short circuit in a printed circuit board. Test signals may be injected at different test points on the circuit board. The distance between each test point and the short circuit may be determined according to how long it takes for a signal reflection at the short circuit to propagate back to each test point. The distances between the various test points and the short circuit can be used to narrow the possible locations of the short circuit or even to pinpoint the location of the short circuit.

Abstract: Improving signal quality in a high-frequency chip package by resistively connecting an open-ended plating stub to ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A conductive first layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A resistor is used to resistively couple the plating stub to a ground layer.

Abstract: A cables for high speed data communications, the cable including a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer. The first inner conductor is substantially parallel to the second inner conductor and to a longitudinal axis. The cable includes a conductive shield wrapped around the first and second inner conductors, with an overlap of the conductive shield along and about the longitudinal axis. The overlap is aligned with a low current plane. The low current plane substantially parallel to the first and second inner conductors, substantially equidistant from the first and second inner conductors, and substantially orthogonal to a plane including the first and second inner conductors.

Abstract: The present invention provides a simple, easy to implement method and apparatus to reduce jitter in a channel and expand the eye width and eye height of the eye pattern of the signal. The method and apparatus of the present invention reduces jitter specific to a channel in a high speed interface. The present invention utilizes a phasing shifting mechanism based on history of the incoming bits at the receiver. The input bits from the channel are shifted in time before getting to the receiver. This approach significantly reduces Intersymbol Interference (ISI) and deterministic jitter, thus opening up the eye width and eye height for a given interface.

Abstract: Packages and methods for mitigating plating stub effects. The semiconductor package includes an interposer substrate having a first side, a second side, a peripheral edge connecting the first side with the second side, a signal line on the first side, and an electrode pad on the first side. A semiconductor element is mounted on the first side of the interposer substrate. The semiconductor element is connected with the electrode pad by the signal line. A terminating resistor is mounted on the interposer substrate. A plating stub, which is located on the interposer substrate, has a first end portion that terminates near the peripheral edge of the interposer substrate and a second end portion that is electrically connected to the electrode. The first end portion is electrically connected through the terminating resistor to an electrical ground.

Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.

Abstract: One embodiment of the invention provides a multi-layered ceramic package. The ceramic package includes a signal layer having a plurality of signal lines and a mesh reference layer parallel to the signal layer. The mesh reference layer includes a plurality of intersecting reference lines of varying reference-line width in the plane of the mesh layer. The mesh reference lines may be widened in locations of probable signal cross-talk. Other embodiments of the invention include software for optimizing a ceramic package design by selectively widening mesh lines in regions of probable cross-talk, and systems for designing and manufacturing such a ceramic package.

Abstract: Off-die termination of memory module signal lines in a computer memory subsystem. The computer memory subsystem includes a memory controller and a DIMM socket installed on a PCB. The memory controller is electrically coupled to the DIMM socket via a memory module signal line. Off-die termination includes detecting, by a termination controller installed on the PCB, no presence of a DIMM in the DIMM socket and, responsive to the detection, activating, by the termination controller, an off-die termination component on the PCB to terminate the memory module signal line.

Abstract: Off-die termination module for terminating memory module signal lines in a computer memory subsystem, the computer memory subsystem including a memory controller and a DIMM socket, the memory controller coupled to the DIMM socket via a memory module signal line, the off-die termination module including: an off-die termination component configured to terminate the memory module signal line upon activation; and a spring loaded notch pin implemented as part of the DIMM socket, the spring loaded notch pin configured to toggle activation of the off-die termination component in dependence upon presence of a DIMM in the DIMM socket including activating the off-die termination component upon removal of a DIMM from the DIMM socket and deactivating the off-die termination component upon installation of a DIMM in the DIMM socket.

Abstract: Embodiments of the invention are directed to transmission cables, and particularly to twinax cables, for transmitting digital data and other information between components in a data processing environment. One embodiment of the invention is directed to an information transmission cable that comprises first and second signal carrying conductors of specified length, each of the signal carrying conductors being disposed to carry information signals and having a longitudinal axis. The embodiment further includes an insulating structure comprising an amount of specified dielectric insulation material, the insulating structure being positioned to surround the first and second signal carrying conductors along their respective lengths, and acting to maintain the first and second signal conductors in spaced apart parallel relationship with each other.

Abstract: An apparatus, system, and method are disclosed for dynamic phase equalization in a communication channel. A transmitter history module stores a plurality of bits from a data stream that is transmitted through the communication channel. A transmitter detection module detects a pre-transition bit of a first value that is preceded in the data stream by at least one bit of the first value and followed by a transition bit with a second value. A driver module transmits the data stream by driving the communication channel. A transition module pre-drives the communication channel to the second voltage of the transition bit during a bit time interval of the pre-transition bit.

Abstract: In one embodiment, a fan is used to generate airflow through a computer chassis to a fan air inlet. An audible frequency component of the airflow is identified and selected. A sound wave is generated having a generated frequency equal to the selected audible frequency component of the airflow. The generated sound wave is introduced into the airflow with the generated frequency out of phase with the audible frequency component of the airflow. The magnitude of the generated frequency may be selected as a function of fan speed and/or air sensed pressure within the airflow. The frequency, phase, and magnitude of the generated sound wave may be selected and enforced by a baseboard management controller.