Abstract: A printed circuit board (‘PCB’) with reduced dielectric loss, including conductive traces disposed upon layers of dielectric material, the layers of dielectric material including core layers and prepreg layers, one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB.

Abstract: Measuring control signal timing for synchronous dynamic random access memory (‘SDRAM’), including combining into a trigger signal for an oscilloscope display control signals of an SDRAM under test, the control signals derived only from a single type of memory operations; and driving, continually during both READ and WRITE operations to and from the SDRAM under test, the oscilloscope display with a memory bus data signal (‘DQ’) and a memory bus clock signal (‘DQS’) from the SDRAM under test.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to via structure utilization in a PCB design and provide a novel and non-obvious method, system and computer program product for impedance discontinuity remediation for via stubs and connectors in a PCB. In one embodiment a method for impedance discontinuity remediation in a PCB can be provided. The method can include configuring a pre-distortion filter to negate an impedance discontinuity in an electrical signal caused by a transmission line with one of a via stub or a connector. The method further can include pre-distortion filtering an electrical signal before transmitting the electrical signal over the transmission line. Finally, the method can include transmitting the pre-distortion filtered electrical signal over the transmission line.

Abstract: A method, system, and computer program product for exploring and optimizing an electrical design space. A computer receiving a design space assigns a plurality of initial values (random or predetermined) for optimizing the design space. A particle swarm containing a plurality of particles is created and an optimization of the design space is then performed using the assigned initial values. Following completion of optimization, the global best and personal best for each particle are updated. Velocity vectors and position vectors of the design space are then updated before the computer performs the optimization process again. The process loops, continually updating global and personal bests and velocity and position vectors until a termination criteria is reached. Upon reaching the termination criteria, the best fitness of each particle of the swarm is assigned as an optimized design space. In an alternate embodiment, the particle with the worst target fitness may be assigned.

Abstract: Techniques for optimizing a Business Process Model (BPM) having at least one work process are presented. At a simulation client, a determination is made whether a simulated business outcome associated with a test BPM satisfies a business value deficiency associated with a current BPM. In response to a determination that the simulated business outcome does not satisfy the business value deficiency, the test BPM is optimized. Once the simulation client determines that the simulated business outcome satisfies the business value deficiency, the test BPM is implemented as an actual BPM. Moreover, an actual business outcome associated with the actual BPM is generated. A determination is made whether the actual business outcome satisfies the simulated business outcome. In response to a determination that the actual business outcome does not satisfy the simulated business outcome, the actual BPM is optimized.

Abstract: One embodiment provides a method of locating a short circuit in a printed circuit board. Test signals may be injected at different test points on the circuit board. The distance between each test point and the short circuit may be determined according to how long it takes for a signal reflection at the short circuit to propagate back to each test point. The distances between the various test points and the short circuit can be used to narrow the possible locations of the short circuit or even to pinpoint the location of the short circuit.

Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.

Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.

Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.

Abstract: Techniques for optimizing a Business Process Model (BPM) having at least one work process are presented. At a simulation client, a determination is made whether a simulated business outcome associated with a test BPM satisfies a business value deficiency associated with a current BPM. In response to a determination that the simulated business outcome does not satisfy the business value deficiency, the test BPM is optimized. Once the simulation client determines that the simulated business outcome satisfies the business value deficiency, the test BPM is implemented as an actual BPM. Moreover, an actual business outcome associated with the actual BPM is generated. A determination is made whether the actual business outcome satisfies the simulated business outcome. In response to a determination that the actual business outcome does not satisfy the simulated business outcome, the actual BPM is optimized.

Abstract: Methods, apparatuses, and computer program products are disclosed for controlling plating stub reflections in a chip package. Embodiments include determining, by a resonance optimizer, performance characteristics of a bond wire, the bond wire connecting a chip to a substrate of a semiconductor chip mount; based on the performance characteristics of the bond wire, selecting, by the resonance optimizer, a line width for an open-ended plating stub, the open-ended plating stub extending from a signal interconnect of the substrate to a periphery of the substrate; and generating, by the resonance optimizer, a design of signal traces for the substrate, the signal traces including the open-ended plating stub with the selected line width.

Abstract: A printed circuit board with reduced signal distortion, including one or more layers of non-conductive substrate upon which are disposed conductive pathways that conduct signals, the signals characterized by distortion at least partly caused by orientation of the conductive pathways on the layers of the printed circuit board, and a periodically patterned reference plane; each conductive pathway that conducts signals oriented orthogonally or diagonally at forty-five degrees with respect to other conductive pathways that conduct signals on the printed circuit board; the periodically patterned reference plane comprising a conductor having discontinuities arranged in a periodically recurring pattern, the pattern of the discontinuities oriented on a surface of a layer of the printed circuit board at an optimum angle, with respect to the conductive pathways that conduct signals on the printed circuit board, that reduces distortion of the signals.

Abstract: In one embodiment, a fan is used to generate airflow through a computer chassis to a fan air inlet. An audible frequency component of the airflow is identified and selected. A sound wave is generated having a generated frequency equal to the selected audible frequency component of the airflow. The generated sound wave is introduced into the airflow with the generated frequency out of phase with the audible frequency component of the airflow. The magnitude of the generated frequency may be selected as a function of fan speed and/or air sensed pressure within the airflow. The frequency, phase, and magnitude of the generated sound wave may be selected and enforced by a baseboard management controller.

Abstract: Customer support involves multiple levels of support, where customer support personnel at higher levels have more experience and a higher cost associated with their services. A random assignment of support personnel to a problem, at lower levels, can lead to multiple call transfers, a customer being put “on hold”, ineffective resource utilization, and high service costs being billed to customers. Functionality can be implemented to assign a support person to resolve the customer's problem based on a multi-dimensional dynamic social network database of resources (e.g., personnel experience, success rate, skill set, social network, etc.) which allows for efficient assignment of support personnel to a problem. Routing a customer call to the most appropriate support person at a given level before determining support personnel at higher levels can ensure optimization in terms of return on investment and resource utilization. Optimally selecting and assigning support personnel can also ensure customer satisfaction.

Abstract: Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations.

Abstract: Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations.

Abstract: Testing an electrical component, the component including a printed circuit board (‘PCB’) with a number of traces, the traces organized in pairs with each trace of a pair carrying current in opposite directions and separated from one another by a substrate layer of the PCB, where testing of the electrical component includes: dynamically and iteratively until a present impedance for a pair of traces of the component is greater than a predetermined threshold impedance: increasing, by an impedance varying device at the behest of a testing device, magnetic field strength of a magnetic field applied to the pair of traces by the impedance varying device, including increasing the present impedance of the pair of traces; measuring, by the testing device, one or more operating parameters; and recording, by the testing device, the measurements of the operating parameters.

Abstract: Improving signal quality in a high-frequency chip package by resistively connecting an open-ended plating stub to ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A conductive first layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A resistor is used to resistively couple the plating stub to a ground layer.

Abstract: A method, computer program product, and apparatus for managing healthcare services are provided. A processor unit receives medical information about a patient. The processor unit generates a group of providers containing a number of providers based on the medical information received about the patient. A number of matches from the number of providers are identified for the patient using the number of providers and based on a number of criteria. A method, computer program product, and apparatus for providing healthcare services are also provided. A processor unit receives medical information about a desired patient. The processor unit generates a group of patients containing a number of patients based on the medical information received about the desired patient. A number of matches from the number of patients are identified using the number of providers and based on a number of criteria.

Abstract: An apparatus having reduced noise coupling includes a core layer having an upper and lower surface, the upper and lower surface each including a copper sheet layer, a pre-preg layer having an upper surface and a lower surface, the upper surface of the pre-preg layer coupled to the lower surface of the core layer, a core insulating layer having an upper surface and a lower surface, the upper surface of the core insulating layer coupled to the lower surface of the pre-preg layer, a return current reference layer disposed on the lower surface of the core insulator layer and high-speed signal traces disposed on the upper surface of the core insulating layer, each of the high speed signal traces disposed on a pedestal defined by a section of the pre-preg layer and the core insulating layer, each pedestal being separated by an air gap disposed between adjacent pedestals.