Patents by Inventor Moises Cases
Moises Cases has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100231209Abstract: Testing an electrical component, the component including a printed circuit board (‘PCB’) with a number of traces, the traces organized in pairs with each trace of a pair carrying current in opposite directions and separated from one another by a substrate layer of the PCB, where testing of the electrical component includes: dynamically and iteratively until a present impedance for a pair of traces of the component is greater than a predetermined threshold impedance: increasing, by an impedance varying device at the behest of a testing device, magnetic field strength of a magnetic field applied to the pair of traces by the impedance varying device, including increasing the present impedance of the pair of traces; measuring, by the testing device, one or more operating parameters; and recording, by the testing device, the measurements of the operating parameters.Type: ApplicationFiled: March 12, 2009Publication date: September 16, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rubina F. Ahmed, Moises Cases, Bradley D. Herrman, Bhyrav M. Mutnury, Pravin Patel, Peter R. Seidel
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Publication number: 20100229131Abstract: A method, system, and computer program product for exploring and optimizing an electrical design space. A computer receiving a design space assigns a plurality of initial values (random or predetermined) for optimizing the design space. A particle swarm containing a plurality of particles is created and an optimization of the design space is then performed using the assigned initial values. Following completion of optimization, the global best and personal best for each particle are updated. Velocity vectors and position vectors of the design space are then updated before the computer performs the optimization process again. The process loops, continually updating global and personal bests and velocity and position vectors until a termination criteria is reached. Upon reaching the termination criteria, the best fitness of each particle of the swarm is assigned as an optimized design space. In an alternate embodiment, the particle with the worst target fitness may be assigned.Type: ApplicationFiled: March 5, 2009Publication date: September 9, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Moises Cases, Jinwoo Choi, Bhyrav Mutnury, Navraj Singh, Caleb J. Wesley
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Patent number: 7791227Abstract: In electronic devices with signal traces positioned between a ground layer and a voltage reference layer, systems and methods are provided for connecting a hot pluggable device to the electronic device in a manner that diminishes signal degradation due to parasitic effects. The first device has a second reference layer near the connector that connects to a second device voltage reference layer maintained at a given voltage level across the connector. In the first device near the connector the signal trace is positioned in between a ground layer of the first device and the second reference layer which is maintained at a given voltage by a voltage regulator of the second device. The signal return current travels past the second reference layer to a first reference layer of the first device which is maintained by the first device's voltage regulator through AC decoupling capacitors minimizing the current return path discontinuity.Type: GrantFiled: September 20, 2007Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Moises Cases, Byron L. Krauter, Bhyrav M. Mutnury, Nam H. Pham
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Patent number: 7759958Abstract: An apparatus, system, and method are disclosed for integrating component testing. A voltage module modifies a reference voltage integral to an electronic device to a plurality of reference voltage values. A test module tests a component of the electronic device at each of the plurality of reference voltage values. In addition, the test module determines a voltage range for the component, wherein the voltage range comprises voltage values between a high voltage failure and a low voltage failure. An optimization module sets the reference voltage value to within the voltage range.Type: GrantFiled: September 21, 2007Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: Moises Cases, Shiva R. Dasari, Erdem Matoglu, Bhyrav M. Mutnury, Nam H. Pham
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Patent number: 7739562Abstract: A programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module. The memory module may emulate multiple selectable memory module types, and may include a complete storage array to provide standard memory module operation.Type: GrantFiled: August 17, 2007Date of Patent: June 15, 2010Assignee: International Business Machines CorporationInventors: Moises Cases, Daniel Mark Dreps, Bhyrav M. Mutnury, Nam H. Pham, Daniel N. De Araujo
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Publication number: 20100138677Abstract: The distribution of data among a plurality of data storage devices may be optimized, in one embodiment, by redistributing the data to move less-active data to lesser performing data storage devices and to move more-active data to higher performing data storage devices. Power consumption in the datacenter may be optimized by selectively reducing power to data storage devices to which less-active data, such as persistent data, has been moved.Type: ApplicationFiled: December 1, 2008Publication date: June 3, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William G. Pagan, Moises Cases, Paul A. Boothe, Carl E. Jones, Bhyrav M. Mutnury
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Patent number: 7730369Abstract: A method for performing memory diagnostics using a programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module.Type: GrantFiled: August 17, 2007Date of Patent: June 1, 2010Assignee: International Business Machines CorporationInventors: Moises Cases, Daniel Mark Dreps, Bhyrav M. Mutnury, Nam H. Pham, Daniel N. De Araujo
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Patent number: 7725783Abstract: The present invention assesses memory (DIMM) strength by calculating frequency content of a radiated field which is collected by an apparatus, such as a dipole antenna. Radiated field is created by accelerated charge, which is a function of the slew rate or DIMM strength. Radiated power is directly proportional to the frequency at which bits are driven. By separating the radiated field from the near field or stored field, the DIMM strength content is isolated from other functional DIMM issues, such as tRCD latency, refresh cycles, addressing mode, etc. By examining the radiated power, the disadvantages of the prior art, such as by probing the DIMM's contacts, are avoided.Type: GrantFiled: July 20, 2007Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: Moises Cases, Daniel N. de Araujo, Bradley D. Herrman, Erdem Matoglu, Bhyrav M. Mutnury, Pravin Patel, Nam H. Pham
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Publication number: 20100118019Abstract: Dynamically managing power consumption of a computer, the computer including two or more graphics adapters, the computer having a number of graphics adapter configurations including one or more of the graphics adapters, where managing power consumption includes: monitoring, by a graphics driver, operation of a current graphics adapter configuration, the operation characterized by a graphics processing load; determining, in dependence upon the graphics processing load, whether operation of the current graphics adapter configuration conforms to predefined graphics processing criteria; if operation conforms, processing graphics, by the graphics adapter, for display with the one or more graphics adapters of the current graphics adapter configuration; and if operation does not conform, processing graphics, by the graphics adapter, for display with the one or more graphics adapters of another graphics adapter configuration.Type: ApplicationFiled: November 12, 2008Publication date: May 13, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Moises Cases, Bhyrav M. Mutnury, William G. Pagan
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Publication number: 20100108350Abstract: Cables and methods of manufacturing cables for high speed data communications, the cable including: a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer, the inner conductors and the dielectric layers parallel with and along a longitudinal axis; and folded conductive shield material wrapped in a rotational direction along and about the longitudinal axis around the inner conductors and the dielectric layers, including overlapped wraps along and about the longitudinal axis, the conductive shield material comprising a first conductive layer and second conductive layer separated by an inner-shield dielectric layer.Type: ApplicationFiled: November 5, 2008Publication date: May 6, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Moises Cases, Daniel N. De Araujo, Bhyrav M. Mutnury, Bruce J. Wilkie
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Publication number: 20100100412Abstract: Customer support involves multiple levels of support, where customer support personnel at higher levels have more experience and a higher cost associated with their services. A random assignment of support personnel to a problem, at lower levels, can lead to multiple call transfers, a customer being put “on hold”, ineffective resource utilization, and high service costs being billed to customers. Functionality can be implemented to assign a support person to resolve the customer's problem based on a multi-dimensional dynamic social network database of resources (e.g., personnel experience, success rate, skill set, social network, etc.) which allows for efficient assignment of support personnel to a problem. Routing a customer call to the most appropriate support person at a given level before determining support personnel at higher levels can ensure optimization in terms of return on investment and resource utilization. Optimally selecting and assigning support personnel can also ensure customer satisfaction.Type: ApplicationFiled: October 20, 2008Publication date: April 22, 2010Applicant: International Business Machines CorporationInventors: Moises Cases, Oliver R. Fasterling, Bhyrav M. Mutnury
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Publication number: 20100099219Abstract: Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations.Type: ApplicationFiled: October 21, 2008Publication date: April 22, 2010Applicant: International Business Machines CorporationInventors: Bhyrav M. Mutnury, Moises Cases, Tae Hong Kim, Nanju Na
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Patent number: 7701222Abstract: A method for testing a printed circuit board to determining the dielectric loss associated with the circuit board material relative to a standard. Dielectric losses in the material generate heat when a high frequency electronic signal, such as a microwave frequency signal, is communicated through a microstrip that is embedded within the printed circuit board. The temperature or spectrum at the surface of printed circuit board is measured and compared against the temperature or spectrum of the standard to determine whether the material under test is acceptable. While various temperature measurement devices may be used, the temperature is preferably measured without contacting the surface, such as using an infrared radiation probe.Type: GrantFiled: October 19, 2007Date of Patent: April 20, 2010Assignee: International Business Machines CorporationInventors: Moises Cases, Bradley Donald Herrman, Kent Barclay Howieson, Erdem Matoglu, Bhyrav Murthy Mutnury, Pravin Patel, Nam Huu Pham, Caleb James Wesley
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Publication number: 20100073893Abstract: Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.Type: ApplicationFiled: September 25, 2008Publication date: March 25, 2010Applicant: International Business Mechines CorporationInventors: Bhyrav Murthy Mutnury, Moises Cases, Nanju Na, Tae Hong Kim
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Publication number: 20100060527Abstract: Embodiments of the invention include electromagnetic band gap (EBG) structures having undulating branches to tune the resulting stopband. A periodically patterned structure of conductive patches are interconnected by the undulating branches. Physical parameters of the undulating branches, such as the number of undulations or “turns” per branch, may be selected to tune the stopband in an effort to achieve a target stopband. Accordingly, embodiments of the invention also include methods of designing and manufacturing an EBG structure using undulating branches.Type: ApplicationFiled: September 10, 2008Publication date: March 11, 2010Applicant: International Business Machines CorporationInventors: Tae Hong Kim, Moises Cases, Bhyrav Murthy Mutnury, Stephen H. Carman
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Publication number: 20100057657Abstract: Embodiments of the present invention address deficiencies of the art in respect to technical support management and provide a novel and non-obvious method, system and computer program product for intelligent problem tracking to optimize technical support. In an embodiment of the invention, a method for intelligent problem tracking can include receiving recorded information of tracked end user behavior collected in an end user computing system while the end user addresses a problem in the end user computing system, determining a level of technical sophistication of the user based upon the recorded information, selecting a technical support level corresponding to the determined level of technical sophistication of the user, and transmitting a resolution to the problem in a message to the end user computing system commensurate with the selected technical support level.Type: ApplicationFiled: August 27, 2008Publication date: March 4, 2010Applicant: International Business Machines CorporationInventors: Paul A. Boothe, Moises Cases, Bhyrav M. Mutnury
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Identifying An Optimized Test Bit Pattern For Analyzing Electrical Communications Channel Topologies
Publication number: 20100014569Abstract: Identifying an optimized test bit pattern for analyzing electrical communications channel topologies, including: ranking according to channel quality, from worst to best, a set of channel topologies for an electrical communications channel; and for each ranked channel topology beginning with the worst, carrying out the following steps in an iterative loop until a concatenated test bit pattern and a previously optimized test bit pattern are functionally equally fit: concatenating to a previously optimized test bit pattern an additional test bit pattern; optimizing the concatenated test bit pattern values for a next ranked channel in the subset, leaving the optimized values of the previously optimized test bit pattern unchanged; and comparing through use of a fitness function the relative qualities of the previously optimized test bit pattern and the optimized concatenated test bit pattern.Type: ApplicationFiled: July 16, 2008Publication date: January 21, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Moises Cases, Bhyrav M. Mutnury, Navraj Singh, Caleb J. Wesley -
Patent number: 7649142Abstract: A cable for high speed data communications and methods for manufacturing such cable are disclosed, the cable including a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer. The cable also includes conductive shield material wrapped in a rotational direction at a rate along and about the longitudinal axis around the inner conductors and the dielectric layers, including overlapped wraps of the conductive shield material along and about the longitudinal axis, the conductive shield material having a variable width. Transmitting signals on the cable including transmitting a balanced signal characterized by a frequency in the range of 7-9 gigahertz on the cable.Type: GrantFiled: March 17, 2009Date of Patent: January 19, 2010Assignee: International Business Machines CorporationInventors: Bruce R. Archambeault, Moises Cases, Samuel R. Connor, Daniel N. de Araujo, Bhyrav M. Mutnury
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Publication number: 20090308649Abstract: A printed circuit board with reduced signal distortion, including one or more layers of non-conductive substrate upon which are disposed conductive pathways that conduct signals, the signals characterized by distortion at least partly caused by orientation of the conductive pathways on the layers of the printed circuit board, and a periodically patterned reference plane; each conductive pathway that conducts signals oriented orthogonally or diagonally at forty-five degrees with respect to other conductive pathways that conduct signals on the printed circuit board; the periodically patterned reference plane comprising a conductor having discontinuities arranged in a periodically recurring pattern, the pattern of the discontinuities oriented on a surface of a layer of the printed circuit board at an optimum angle, with respect to the conductive pathways that conduct signals on the printed circuit board, that reduces distortion of the signals.Type: ApplicationFiled: June 17, 2008Publication date: December 17, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Moises Cases, Tae H. Kim, Bhyrav M. Mutnury
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Publication number: 20090307636Abstract: A method of optimizing a very large scale integrated circuit design takes a circuit description which includes interconnected circuit components and characteristic variables assigned to the circuit components such as environmental, operational or process parameters, computes a first solution for the characteristic variables using a statistical analysis, and then computes a second solution for the characteristic variables using an evolutionary analysis seeded by the first solution. In the exemplary implementation the statistical analysis is a central composite design (CCD) and the evolutionary analysis is a genetic algorithm. Best case and worst case CCD solutions may be used to seed separate genetic algorithm runs and derive global best case and global worst case solutions. These solutions may be compared for sensitivity analysis. The method thereby provides significant reduction in time-to-solution with accurate simulation results.Type: ApplicationFiled: June 5, 2008Publication date: December 10, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Moises Cases, Jinwoo Choi, Bhyrav M. Mutnury, Caleb J. Wesley