Patents by Inventor Munaf Rahimo

Munaf Rahimo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130228823
    Abstract: A reverse-conducting semiconductor device (RC-IGBT) including a freewheeling diode and an insulated gate bipolar transistor (IGBT), and a method for making the RC-IGBT are provided. A first layer of a first conductivity type is created on a collector side before a second layer of a second conductivity type is created on the collector side. An electrical contact in direct electrical contact with the first and second layers is created on the collector side. A shadow mask is applied on the collector side, and a third layer of the first conductivity type is created through the shadow mask. At least one electrically conductive island, which is part of a second electrical contact in the finalized RC-IGBT, is created through the shadow mask. The island is used as a mask for creating the second layer, and those parts of the third layer which are covered by the island form the second layer.
    Type: Application
    Filed: April 11, 2013
    Publication date: September 5, 2013
    Applicant: ABB TECHNOLOGY AG
    Inventors: Munaf RAHIMO, Wolfgang Janisch, Eustachio Faggiano
  • Patent number: 8508016
    Abstract: A bipolar punch-through semiconductor device has a semiconductor substrate, which includes at least a two-layer structure, a first main side with a first electrical contact, and a second main side with a second electrical contact. One of the layers in the two-layer structure is a base layer of the first conductivity type. A buffer layer of the first conductivity type is arranged on the base layer. A first layer includes alternating first regions of the first conductivity type and second regions of the second conductivity type. The first layer is arranged between the buffer layer and the second electrical contact. The second regions are activated regions with a depth of at maximum 2 ?m and a doping profile, which drops from 90% to 10% of the maximum doping concentration within at most 1 ?m.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: August 13, 2013
    Assignee: ABB Technology AG
    Inventors: Munaf Rahimo, Ulrich Schlapbach, Arnost Kopta
  • Patent number: 8501548
    Abstract: A method for producing a semiconductor device such as a RC-IGBT or a BIGT having a patterned surface wherein partial regions doped with dopants of a first conductivity type and regions doped with dopants of a second conductivity type are on a same side of a semiconductor substrate is proposed. An exemplary method includes: (a) implanting dopants of the first conductivity type and implanting dopants of the second conductivity type into the surface to be patterned; (b) locally activating dopants of the first conductivity type by locally heating the partial region of the surface to be patterned to a first temperature (e.g., between 900 and 1000° C.) using a laser beam similar to those used in laser annealing; and (c) activating the dopants of the second conductivity type by heating the substrate to a second temperature lower than the first temperature (e.g., to a temperature below 600° C.).
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: August 6, 2013
    Assignee: ABB Technology AG
    Inventors: Jan Vobecky, Munaf Rahimo
  • Patent number: 8501586
    Abstract: In order to produce a power semiconductor for operation at high blocking voltages, there is produced on a lightly doped layer having a doping of a first charge carrier type a medium-doped layer of the same charge carrier type. A highly doped layer is produced at that side of the medium-doped layer which is remote from the lightly doped layer, of which highly doped layer a part with high doping that remains in the finished semiconductor forms a second stop layer, wherein the doping of the highly doped layer is higher than the doping of the medium-doped layer. An electrode is subsequently indiffused into the highly doped layer. The part with low doping that remains in the finished semiconductor forms the drift layer and the remaining medium-doped part forms the first stop layer.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: August 6, 2013
    Assignee: ABB Technology AG
    Inventors: Munaf Rahimo, Arnost Kopta, Stefan Linder
  • Patent number: 8461622
    Abstract: A reverse-conducting semiconductor device includes a freewheeling diode and an insulated gate bipolar transistor (IGBT) on a common wafer. Part of the wafer forms a base layer with a base layer thickness. The IGBT includes a collector side and an emitter side arranged on opposite sides of the wafer. A first layer of a first conductivity type and a second layer of a second conductivity type are alternately arranged on the collector side. The first layer includes at least one first region with a first region width and at least one first pilot region with a first pilot region width. The second layer includes at least one second region with a second region width and at least one second pilot region with a second pilot region width. Each second region width is equal to or larger than the base layer thickness, whereas each first region width is smaller than the base layer thickness. Each second pilot region width is larger than each first pilot region width.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: June 11, 2013
    Assignee: ABB Technology AG
    Inventors: Arnost Kopta, Munaf Rahimo
  • Patent number: 8450777
    Abstract: A reverse-conducting insulated gate bipolar transistor includes a wafer of first conductivity type with a second layer of a second conductivity type and a third layer of the first conductivity type. A fifth electrically insulating layer partially covers these layers. An electrically conductive fourth layer is electrically insulated from the wafer by the fifth layer. The third through the fifth layers form a first opening above the second layer. A sixth layer of the second conductivity type and a seventh layer of the first conductivity type are arranged alternately in a plane on a second side of the wafer. A ninth layer is formed by implantation of ions through the first opening using the fourth and fifth layers as a first mask.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: May 28, 2013
    Assignee: ABB Technology AG
    Inventors: Munaf Rahimo, Jan Vobecky, Arnost Kopta
  • Patent number: 8450793
    Abstract: A controlled-punch-through semiconductor device with a four-layer structure is disclosed which includes layers of different conductivity types, a collector on a collector side, and an emitter on an emitter side which lies opposite the collector side. The semiconductor device can be produced by a method performed in the following order: producing layers on the emitter side of wafer of a first conductivity type; thinning the wafer on a second side; applying particles of the first conductivity type to the wafer on the collector side for forming a first buffer layer having a first peak doping concentration in a first depth, which is higher than doping of the wafer; applying particles of a second conductivity type to the wafer on the second side for forming a collector layer on the collector side; and forming a collector metallization on the second side.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: May 28, 2013
    Assignee: ABB Technology AG
    Inventors: Munaf Rahimo, Jan Vobecky, Wolfgang Janisch, Arnost Kopta, Frank Ritchie
  • Patent number: 8435863
    Abstract: A reverse-conducting semiconductor device (RC-IGBT) including a freewheeling diode and an insulated gate bipolar transistor (IGBT), and a method for making the RC-IGBT are provided. A first layer of a first conductivity type is created on a collector side before a second layer of a second conductivity type is created on the collector side. An electrical contact in direct electrical contact with the first and second layers is created on the collector side. A shadow mask is applied on the collector side, and a third layer of the first conductivity type is created through the shadow mask. At least one electrically conductive island, which is part of a second electrical contact in the finalized RC-IGBT, is created through the shadow mask. The island is used as a mask for creating the second layer, and those parts of the third layer which are covered by the island form the second layer.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: May 7, 2013
    Assignee: ABB Technology AG
    Inventors: Munaf Rahimo, Wolfgang Janisch, Eustachio Faggiano
  • Patent number: 8415239
    Abstract: An exemplary method is disclosed for manufacturing a power semiconductor device which has a first electrical contact on a first main side and a second electrical contact on a second main side opposite the first main side and at least a two-layer structure with layers of different conductivity types, and includes providing an n-doped wafer and creating a surface layer of palladium particles on the first main side. The wafer is irradiated on the first main side with ions. Afterwards, the palladium particles are diffused into the wafer at a temperature of not more than 750° C., by which diffusion a first p-doped layer is created. Then, the first and second electrical contacts are created. At least the irradiation with ions is performed through a mask.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: April 9, 2013
    Assignee: ABB Technology AG
    Inventors: Jan Vobecky, Munaf Rahimo
  • Patent number: 8395244
    Abstract: A fast recovery diode includes an n-doped base layer having a cathode side and an anode side opposite the cathode side. A p-doped anode layer is arranged on the anode side. The anode layer has a doping profile and includes at least two sublayers. A first one of the sublayers has a first maximum doping concentration, which is between 2*1016 cm?3 and 2*1017 cm?3 and which is higher than the maximum doping concentration of any other sublayer. A last one of the sublayers has a last sublayer depth, which is larger than any other sublayer depth. The last sublayer depth is between 90 to 120 ?m. The doping profile of the anode layer declines such that a doping concentration in a range of 5*1014 cm?3 and 1*1015 cm?3 is reached between a first depth, which is at least 20 ?m, and a second depth, which is at maximum 50 ?m. Such a profile of the doping concentration is achieved by using aluminum diffused layers as the at least two sublayers.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: March 12, 2013
    Assignee: ABB Technology AG
    Inventors: Jan Vobecky, Kati Hemmann, Hamit Duran, Munaf Rahimo
  • Publication number: 20130026537
    Abstract: A power semiconductor device is disclosed with layers of different conductivity types between an emitter electrode on an emitter side and a collector electrode on a collector side. The device can include a drift layer, a first base layer in direct electrical contact to the emitter electrode, a first source region embedded into the first base layer which contacts the emitter electrode and has a higher doping concentration than the drift layer, a first gate electrode in a same plane and lateral to the first base layer, a second base layer in the same plane and lateral to the first base layer, a second gate electrode on top of the emitter side, and a second source region electrically insulated from the second base layer, the second source region and the drift layer by a second insulating layer.
    Type: Application
    Filed: September 24, 2012
    Publication date: January 31, 2013
    Applicant: ABB Technology AG
    Inventors: Munaf RAHIMO, Arnost Kopta, Christoph Von Arx, Maxi Andenna
  • Patent number: 8324062
    Abstract: A method of manufacturing a power semiconductor device is provided. A first oxide layer is produced on a first main side of a substrate of a first conductivity type. A structured gate electrode layer with at least one opening is then formed on the first main side on top of the first oxide layer. A first dopant of the first conductivity type is implanted into the substrate on the first main side using the structured gate electrode layer as a mask, and the first dopant is diffused into the substrate. A second dopant of a second conductivity type is then implanted into the substrate on the first main side, and the second dopant is diffused into the substrate. After diffusing the first dopant into the substrate and before implanting the second dopant into the substrate, the first oxide layer is partially removed. The structured gate electrode layer can be used as a mask for implanting the second dopant.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: December 4, 2012
    Assignee: ABB Technology AG
    Inventors: Arnost Kopta, Munaf Rahimo
  • Publication number: 20120299054
    Abstract: A power semiconductor device includes a four-layer structure having layers arranged in order: (i) a cathode layer of a first conductivity type with a central area being surrounded by a lateral edge, the cathode layer being in direct electrical contact with a cathode electrode, (ii) a base layer of a second conductivity type, (iii) a drift layer of the first conductivity typehaving a lower doping concentration than the cathode layer, and (iv) an anode layer of the second conductivity type which is in electrical contact with an anode electrode. The base layer includes a first layer as a continuous layer contacting the central area of the cathode layer. A resistance reduction layer, in which the resistance at the junction between the lateral edge of the cathode and base layers is reduced, is arranged between the first layer and the cathode layer and covers the lateral edge of the cathode layer.
    Type: Application
    Filed: June 22, 2012
    Publication date: November 29, 2012
    Applicant: ABB Technology AG
    Inventor: Munaf RAHIMO
  • Publication number: 20120280272
    Abstract: A maximum-punch-through semiconductor device such as an insulated gate bipolar transistor (IGBT) or a diode, and a method for producing same are disclosed. The MPT semiconductor device can include at least a two-layer structure having an emitter metallization, a channel region, a base layer with a predetermined doping concentration ND, a buffer layer and a collector metallization. A thickness W of the base layer can be determined by: W = V bd + V pt 4010 ? ? kV ? ? cm - 5 / 8 * ( N D ) 1 / 8 wherein a punch-through voltage Vpt of the semiconductor device is between 70% and 99% of a break down voltage Vbd of the semiconductor device, and wherein the thickness W is a minimum thickness of the base layer between a junction to the channel region and the buffer layer.
    Type: Application
    Filed: May 10, 2012
    Publication date: November 8, 2012
    Applicant: ABB Technology AG
    Inventors: Munaf RAHIMO, Arnost KOPTA, Jan VOBECKY, Wolfgang JANISCH
  • Publication number: 20120199954
    Abstract: A semiconductor device which provides a small and simple design with efficient cooling. A first electrically conducting cooling element is in contact with first electrodes of semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the first electrodes of the semiconductor elements to an external apparatus. A second electrically conducting cooling element is in contact with second electrodes of the semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the second electrodes of the semiconductor elements to an external apparatus. The semiconductor device includes an interface which is electrically connected to gates of the semiconductor elements for external control of respective states of the semiconductor elements.
    Type: Application
    Filed: February 7, 2012
    Publication date: August 9, 2012
    Applicant: ABB RESEARCH LTD
    Inventors: Slavo KICIN, Nicola Schulz, Munaf Rahimo, Raffael Schnell
  • Patent number: 8212283
    Abstract: A reverse-conducting semiconductor device is disclosed with an electrically active region, which includes a freewheeling diode and an insulated gate bipolar transistor on a common wafer. Part of the wafer forms a base layer with a base layer thickness. A first layer of a first conductivity type with at least one first region and a second layer of a second conductivity type with at least one second and third region are alternately arranged on the collector side. Each region has a region area with a region width surrounded by a region border. The RC-IGBT can be configured such that the following exemplary geometrical rules are fulfilled: each third region area is an area, in which any two first regions have a distance bigger (i.e.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: July 3, 2012
    Assignee: ABB Technology AG
    Inventors: Liutauras Storasta, Munaf Rahimo, Christoph Von Arx, Arnost Kopta, Raffael Schnell
  • Publication number: 20110278694
    Abstract: A bipolar punch-through semiconductor device has a semiconductor substrate, which includes at least a two-layer structure, a first main side with a first electrical contact, and a second main side with a second electrical contact. One of the layers in the two-layer structure is a base layer of the first conductivity type. A buffer layer of the first conductivity type is arranged on the base layer. A first layer includes alternating first regions of the first conductivity type and second regions of the second conductivity type. The first layer is arranged between the buffer layer and the second electrical contact. The second regions are activated regions with a depth of at maximum 2 ?m and a doping profile, which drops from 90% to 10% of the maximum doping concentration within at most 1 ?m.
    Type: Application
    Filed: June 15, 2011
    Publication date: November 17, 2011
    Applicant: ABB Technology AG
    Inventors: Munaf RAHIMO, Ulrich Schlapbach, Arnost Kopta
  • Publication number: 20110204414
    Abstract: A reverse-conducting semiconductor device includes a freewheeling diode and an insulated gate bipolar transistor (IGBT) on a common wafer. Part of the wafer forms a base layer with a base layer thickness. The IGBT includes a collector side and an emitter side arranged on opposite sides of the wafer. A first layer of a first conductivity type and a second layer of a second conductivity type are alternately arranged on the collector side. The first layer includes at least one first region with a first region width and at least one first pilot region with a first pilot region width. The second layer includes at least one second region with a second region width and at least one second pilot region with a second pilot region width. Each second region width is equal to or larger than the base layer thickness, whereas each first region width is smaller than the base layer thickness. Each second pilot region width is larger than each first pilot region width.
    Type: Application
    Filed: May 2, 2011
    Publication date: August 25, 2011
    Applicant: ABB Technology AG
    Inventors: Arnost KOPTA, Munaf Rahimo
  • Patent number: 7989878
    Abstract: An n-channel insulated gate semiconductor device with an active cell (5) comprising a p channel well region (6) surrounded by an n type third layer (8), the device further comprising additional well regions (11) formed adjacent to the channel well region (6) outside the active semiconductor cell (5) has enhanced safe operating are capability. The additional well regions (11) outside the active cell (5) do not affect the active cell design in terms of cell pitch, i.e. the design rules for cell spacing, and hole drainage between the cells, hence resulting in optimum carrier profile at the emitter side for low on-state losses.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: August 2, 2011
    Assignee: ABB Schweiz AG
    Inventor: Munaf Rahimo
  • Publication number: 20110136300
    Abstract: A method for producing a semiconductor device such as a RC-IGBT or a BIGT having a patterned surface wherein partial regions doped with dopants of a first conductivity type and regions doped with dopants of a second conductivity type are on a same side of a semiconductor substrate is proposed. An exemplary method includes: (a) implanting dopants of the first conductivity type and implanting dopants of the second conductivity type into the surface to be patterned; (b) locally activating dopants of the first conductivity type by locally heating the partial region of the surface to be patterned to a first temperature (e.g., between 900 and 1000° C.) using a laser beam similar to those used in laser annealing; and (c) activating the dopants of the second conductivity type by heating the substrate to a second temperature lower than the first temperature (e.g., to a temperature below 600° C.).
    Type: Application
    Filed: November 22, 2010
    Publication date: June 9, 2011
    Applicant: ABB Technology AG
    Inventors: Jan VOBECKY, Munaf Rahimo