Abstract: A manufacturing method of a thin film transistor. An amorphous silicon thin film is formed on an insulating substrate, and is crystallized by a lateral solidification process with illumination of laser beams into the amorphous silicon thin film to form a polysilicon thin film. Next, protrusion portions protruding from the surface of the polysilicon thin film are removed by plasma dry-etching using a gas mixture including Cl2, SF6 and Ar at the ratio of 3:1:2 to smooth the surface of the polysilicon thin film, and the semiconductor layer is formed by patterning the polysilicon thin film. A gate insulating film covering the semiconductor layer is formed and a gate electrode is formed on the gate insulating film opposite the semiconductor layer.

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: depositing an amorphous silicon layer on an insulating substrate; converting the amorphous silicon layer to a polysilicon layer by a plurality of laser shots using a mask; forming a gate insulating layer on the polysilicon layer; forming a plurality of gate lines on the gate insulating layer; forming a first interlayer insulating layer on the gate lines; forming a plurality of data lines on the first interlayer insulating layer; forming a second interlayer insulating layer on the data lines; and forming a plurality of pixel electrodes on the second interlayer insulating layer, wherein the mask comprises a plurality of transmitting areas and a plurality of blocking areas arranged in a mixed manner.

Abstract: The present invention relates to a thin film transistor and a liquid crystal display. A gate electrode is formed to include at least one portion extending in a direction perpendicular to a gain growing direction in order to make electrical charge mobility of TFTs uniform without increasing the size of the driving circuit. A thin film transistor according to the present invention includes a semiconductor pattern a thin film of poly-crystalline silicon containing grown grains on the insulating substrate. The semiconductor pattern includes a channel region and source and drain regions opposite with respect to the channel region. A gate insulating layer covers the semiconductor pattern. On the gate insulating layer, a gate electrode including at least one portion extending in a direction crossing the growing direction of the grains and overlapping the channel region is formed.

Abstract: A mask for forming polysilicon has a first slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a second slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a third slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, and a fourth slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width. The slit patterns arranged at the first to fourth slit regions are sequentially enlarged in width in the horizontal direction in multiple proportion to the width d of the slit pattern at the first slit region. The centers of the slit patterns arranged at the first to fourth slit regions in the horizontal direction are placed at the same line.

Abstract: A wearable inhalation filter for a user to wear in her or his nostrils is provided. The filter includes two nose rings that are inserted into the nostrils, and a bridge that connects the nose rings. The nose ring includes a filter assembly for filtering air being inhaled, and the length of the bridge between the two nose rings is adjustable. The filter assembly includes a filter web having a plurality of pores, the size of which is from 4 to 25 ?. The filter web protrudes from the nose ring, and is corrugated to give wider filter area and to ease breathing. The bridge can rotate with respect to the nose ring. The distance between the bridge and the nose ring can be adjusted.

Abstract: In a method of manufacturing a thin film transistor according to the present invention, an amorphous silicon thin film is firstly formed on an insulating substrate and a planarization layer is formed thereon. Thereafter, the amorphous silicon thin film is crystallized by a solidification process using a laser-irradiation to form a polysilicon thin film. Next, the polysilicon thin film and the planarization layer are patterned to form a semiconductor layer, and a gate insulating layer covering the semiconductor layer is formed. Then, a gate electrode is formed on the gate insulating layer opposite the semiconductor layer. Next, impurities are implanted into the semiconductor layer to form a source region and a drain region opposite each other with respect to the gate electrode, and a source electrode and a drain electrode electrically connected to the source region and the drain region, respectively, are formed.

Abstract: A thin film transistor array panel is provided, which includes: a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes; a gate driving circuit supplying gate signals to the gate lines; and a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments.

Abstract: A mask for crystallization of amorphous silicon to polysilicon is provided. The mask includes a plurality of slit patterns for defining regions to be illuminated. The plurality of slit patterns are formed along a longitudinal first direction and the mask moves along a longitudinal second direction. The first longitudinal direction is substantially perpendicular to the second longitudinal direction. Each of the split patterns is deviated apart by substantially a same distance from another. Thus, the polysilicon using the mask are grown to be isotropic with respect to the horizontal and vertical directions.

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: depositing an amorphous silicon layer on an insulating substrate; converting the amorphous silicon layer to a polysilicon layer by a plurality of laser shots using a mask; forming a gate insulating layer on the polysilicon layer; forming a plurality of gate lines on the gate insulating layer; forming a first interlayer insulating layer on the gate lines; forming a plurality of data lines on the first interlayer insulating layer; forming a second interlayer insulating layer on the data lines; and forming a plurality of pixel electrodes on the second interlayer insulating layer, wherein the mask comprises a plurality of transmitting areas and a plurality of blocking areas arranged in a mixed manner.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.

Abstract: In a method of manufacturing a thin film transistor according to the present invention, an amorphous silicon thin film is firstly formed on an insulating substrate and a planarization layer is formed thereon. Thereafter, the amorphous silicon thin film is crystallized by a solidification process using a laser-irradiation to form a polysilicon thin film. Next, the polysilicon thin film and the planarization layer are patterned to form a semiconductor layer, and a gate insulating layer covering the semiconductor layer is formed. Then, a gate electrode is formed on the gate insulating layer opposite the semiconductor layer. Next, impurities are implanted into the semiconductor layer to form a source region and a drain region opposite each other with respect to the gate electrode, and a source electrode and a drain electrode electrically connected to the source region and the drain region, respectively, are formed.

Abstract: First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.

Abstract: First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.

Abstract: A mask for crystallization of amorphous silicon to polysilicon is provided. The mask includes a plurality of slit patterns for defining regions to be illuminated. The plurality of slit patterns are formed along a longitudinal first direction and the mask moves along a longitudinal second direction. The first longitudinal direction is substantially perpendicular to the second longitudinal direction. Each of the split patterns is deviated apart by substantially a same distance from another. Thus, the polysilicon using the mask are grown to be isotropic with respect to the horizontal and vertical directions.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with An Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.