Abstract: The present invention relates to a thin film transistor and a liquid crystal display. A gate electrode is formed to include at least one portion extending in a direction perpendicular to a gain growing direction in order to make electrical charge mobility of TFTs uniform without increasing the size of the driving circuit. A thin film transistor according to the present invention includes a semiconductor pattern a thin film of poly-crystalline silicon containing grown grains on the insulating substrate. The semiconductor pattern includes a channel region and source and drain regions opposite with respect to the channel region. A gate insulating layer covers the semiconductor pattern. On the gate insulating layer, a gate electrode including at least one portion extending in a direction crossing the growing direction of the grains and overlapping the channel region is formed.

Abstract: A plurality laser beams generated by a plurality of beam generators are synthesized by a beam synthesizer. The synthesized beam is splitted into a plurality of beamlets and provided for a plurality of optical units controlling the beamlets. Each beamlet controlled by each optical unit is illuminated onto an amorphous silicon layer deposited on a substrate that is mounted on a plurality of stages to be polycrystallized.

Abstract: A wire for a liquid crystal display has a dual-layered structure comprising a first layer made of molybdenum or molybdenum alloy, and a second layer made of molybdenum nitride or molybdenum alloy nitride. To manufacture the wire, a layer made of either a molybdenum or a molybdenum alloy, and another layer one of either a molybdenum nitride or molybdenum alloy nitride by using reactive sputtering method are deposited in sequence, and then patterned simultaneously. The target for reactive sputtering is made of either molybdenum or molybdenum alloy, and the molybdenum alloy comprises one selected from the group consisting of tungsten, chromium, zirconium, and nickel of the content ratio of 0.1 to less than 20 atm % of. The reactive gas mixture for reactive sputtering includes an argon gas and inflow amount of the nitrogen gas is at least 50% of argon gas, to minimize the etch rate of the molybdenum nitride layer or the molybdenum alloy nitride layer for ITO etchant.

Abstract: An array substrate includes a base substrate, a switching element, and a pixel electrode. The switching element is on the base substrate. The switching element includes a poly silicon pattern having at least one block. Grains are formed in each of the at least one block that are extended in a plurality of directions. The pixel electrode is electrically connected to the switching element. Therefore, current mobility and design margin of the switching element are improved.

Abstract: A crystallization mask for laser illumination for converting amorphous silicon into polysilicon is provided, which includes: a plurality of transmissive areas having a plurality of first slits for adjusting energy of the laser illumination passing through the mask; and an opaque area.

Abstract: A thin film transistor array panel is provided, which includes: a substrate including a plurality of pixel areas; a semiconductor layer formed on the substrate and including a plurality of pairs of first and second semiconductor portions in respective pixel areas; a first insulating layer formed on the semiconductor layer; a gate wire formed on the first insulating layer; a second insulating layer formed on the gate wire; a data wire formed on the second insulating layer; a third insulating layer formed on the data wire; a pixel electrode formed on the third insulating layer and connected to the data wire, wherein width and length of at least one of the first and the second semiconductor portions vary between at least two pixel areas.

Abstract: A thin film transistor array panel includes a substrate, a data line and a gate electrode formed on the substrate, a insulating layer formed on the data line and the gate electrode, a semiconductor layer formed on the insulating layer, a drain electrode and a source electrode formed on the semiconductor layer, a passivation layer formed on the drain electrode and the source electrode including a first contact hole to expose a portion of the data line, a second contact hole to expose a portion of the source electrode, a third contact hole to expose a portion of the drain electrode, and a fourth contact hole to expose a portion of gate electrode, a first connector formed on the passivation layer and connected to the data line and the source electrode through the first contact hole and the second contact hole, a gate line formed on the passivation layer and connected to the gate electrode through the fourth contact hole, and a pixel electrode connected to the drain electrode through the third contact hole.

Abstract: A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming an ohmic contact layer on the semiconductor layer, and forming a data line including a source electrode and a drain electrode on the ohmic contact layer. The method further includes depositing a conductive film on the data line and the drain electrode, forming a first photoresist on the conductive film, etching the conductive film using the first photoresist as a mask to form a pixel electrode at least connected to the drain electrode, depositing a passivation layer, and removing the first photoresist to form a passivation member.

Abstract: A display device includes a data driver, an inverter, a display panel, and an intercept unit. The data driver provides an image signal and the scan driver generates a control signal corresponding to the image signal. The inverter provides an inverted control signal. The display panel has a PMOS transistor that provides the image signal to a pixel electrode based on the inverted control signal. The interception unit intercepts an abnormal signal that is forwarded to the PMOS transistor. Therefore, a signal having an abnormal voltage level may be interrupted to prevent display defects resulting from the abnormal voltage level.

Abstract: A silicon crystallization system includes a beam generator generating a laser beam, first and second optical units for controlling the laser beam from the beam generator; and a stage for mounting a panel including an amorphous silicon layer to be polycrystallized by the laser beam from the optical units. The first optical unit makes the laser beam have a transverse edge and a longitudinal edge longer than the transverse edge, and the second optical unit makes the laser beam have a transverse edge and a longitudinal edge shorter than the transverse edge.

Abstract: A device for irradiating a laser beam onto an amorphous silicon thin film formed on a substrate. The device includes: a stage mounting the substrate; a laser oscillator for generating a laser beam; a projection lens for focusing and guiding the laser beam onto the thin film; a reflector for reflecting the laser beam guided onto the thin film; a controller for controlling a position of the reflector, and an absorber for absorbing the laser beam reflected by the reflector.

Abstract: A thin film transistor array panel is provided, which includes: a substrate including a plurality of pixel areas; a semiconductor layer formed on the substrate and including a plurality of pairs of first and second semiconductor portions in respective pixel areas; a first insulating layer formed on the semiconductor layer; a gate wire formed on the first insulating layer; a second insulating layer formed on the gate wire; a data wire formed on the second insulating layer; a third insulating layer formed on the data wire; a pixel electrode formed on the third insulating layer and connected to the data wire, wherein width and length of at least one of the first and the second semiconductor portions vary between at least two pixel areas.

Abstract: In an array substrate and a display apparatus, a pixel part has a plurality of gate lines, a plurality of data lines, and a plurality of pixels electrically connected to the gate and data lines. A driving circuit drives the pixel part electrically connected to a first end of the gate lines. An inspection circuit is electrically connected to a second end of the gate lines, and inspects the pixel part in response to an inspection signal externally provided. Thus, positions and causes for defects of the pixel part may be accurately detected, thereby improving inspecting efficiency.

Abstract: In a method of manufacturing a thin film transistor according to the present invention, an amorphous silicon thin film is firstly formed on an insulating substrate and a planarization layer is formed thereon. Thereafter, the amorphous silicon thin film is crystallized by a solidification process using a laser-irradiation to form a polysilicon thin film. Next, the polysilicon thin film and the planarization layer are patterned to form a semiconductor layer, and a gate insulating layer covering the semiconductor layer is formed. Then, a gate electrode is formed on the gate insulating layer opposite the semiconductor layer. Next, impurities are implanted into the semiconductor layer to form a source region and a drain region opposite each other with respect to the gate electrode, and a source electrode and a drain electrode electrically connected to the source region and the drain region, respectively, are formed.

Abstract: A display device according to an exemplary embodiment of the present invention includes: a plurality of pixels including switching elements; a plurality of pairs of first and second gate lines connected to the switching elements and separated from each other, transmitting a gate-on voltage for turning on the switching elements; and a plurality of data lines connected to the switching elements, transmitting data signals, wherein each pair of first and second gate lines is disposed between two adjacent pixel rows and is connected to one of the pixel rows.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 ??cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.

Abstract: An optic mask for crystallizing amorphous silicon comprises a first slit region including a plurality of slits regularly arranged for defining incident region of laser beam, wherein the slits of the first slit region are formed to slope by a predetermined angle to the direction of transfer of the optic mask in crystallization process, and wherein the slits of the first slit region includes a first slit having a first length and a second slit having a second length which is longer than the first length.

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: depositing an amorphous silicon layer on an insulating substrate; converting the amorphous silicon layer to a polysilicon layer by a plurality of laser shots using a mask; forming a gate insulating layer on the polysilicon layer; forming a plurality of gate lines on the gate insulating layer; forming a first interlayer insulating layer on the gate lines; forming a plurality of data lines on the first interlayer insulating layer; forming a second interlayer insulating layer on the data lines; and forming a plurality of pixel electrodes on the second interlayer insulating layer, wherein the mask comprises a plurality of transmitting areas and a plurality of blocking areas arranged in a mixed manner.

Abstract: A crystallization mask for laser illumination for converting amorphous silicon into polysilicon is provided, which includes: a plurality of transmissive areas having a plurality of first slits for adjusting energy of the laser illumination passing through the mask; and an opaque area.

Abstract: A system and method of forming a thin film on a semiconductor wafer includes: a reaction tube adapted to provide a sealed space to process a wafer; dual wafer loading boats including a first wafer loading boat and a second wafer loading boat, the first wafer loading boat arranged within the sealed space of the reaction tube, the second wafer loading boat arranged adjacent to either an internal side or an external side of the first wafer loading boat; a gap adjusting unit arranged at a lower portion of the dual wafer loading boats; and a gas supplying unit adapted to supply at least one process gas to the reaction chamber.