Patents by Inventor Nan Wang

Nan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220005931
    Abstract: A semiconductor device and a forming method thereof are provided. The semiconductor device includes a substrate, a fin located on the substrate, and a gate structure located on the substrate and across the fin. The fin includes a first region, and the fin of the first region includes a gate groove and a channel layer located between adjacent gate grooves. The gate structure covers a sidewall and a top of the fin of the first region, fills the gate groove and surrounds the channel layer. A width of the gate structure located in the gate groove is smaller than a width of the gate structure located on the top of the fin of the first region.
    Type: Application
    Filed: May 10, 2021
    Publication date: January 6, 2022
    Inventor: Nan WANG
  • Patent number: 11217681
    Abstract: Fabrication method and semiconductor device are provided. The method includes: providing a base substrate including a first region and a second region adjacent to the first region, with first fins disposed on the base substrate in the first region and on the base substrate in the second region, and initial openings disposed between adjacent first fins; forming sidewall spacers on sidewalls of the first fins to form openings from the initial openings; and forming the second fins in the openings of the second region.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: January 4, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Publication number: 20210407846
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, including a plurality of protrusions; a plurality of fins formed over the substrate and aligned with the plurality of protrusions; and an isolation structure formed on the substrate and between the protrusions and the fins. An orthographic projection of each of the plurality of fins and an orthographic projection of a corresponding protrusion of the plurality of protrusions on the substrate coincide with each other.
    Type: Application
    Filed: September 10, 2021
    Publication date: December 30, 2021
    Inventor: Nan WANG
  • Publication number: 20210398974
    Abstract: A semiconductor device and a fabrication method are provided. The semiconductor device includes: a base substrate; a gate structure on the base substrate including a first portion in a first region and a second portion in a second region; and a separation section in the first portion of the gate structure in the first region. A length of the first portion of the gate structure in the first region is larger than a length of the second portion of the gate structure in the second region. A top surface of the separation section is higher than a top surface of the gate structure.
    Type: Application
    Filed: April 19, 2021
    Publication date: December 23, 2021
    Inventor: Nan WANG
  • Publication number: 20210399105
    Abstract: A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a base substrate; a gate structure on the base substrate, including a first portion in a first region and a second portion in a second region; and one or more stop layers on the base substrate and located in the first portion of the gate structure in the first region. A length of the first portion of the gate structure in the first region is larger than a length of the second portion of the gate structure in the second region.
    Type: Application
    Filed: April 15, 2021
    Publication date: December 23, 2021
    Inventor: Nan WANG
  • Patent number: 11205703
    Abstract: A semiconductor device and fabrication method thereof are provided. The method includes: providing a gate structure, a first dielectric layer, and source/drain doped layers on a base substrate and in the base substrate on sides of the gate structure; forming a mask layer on the gate structure between the source/drain doped layers; forming a second dielectric layer on the first dielectric layer and exposing the mask layer; etching the second dielectric layer and the first dielectric layer using the mask layer as an etch mask, to form first grooves on the sides of the gate structure and exposing the source/drain doped layers; forming a first conductive structure in each first groove; patterning the mask layer to form a second groove in the mask layer to expose the gate structure at the bottom of the second groove; and forming a spacer on sidewalls of the second groove.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: December 21, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Publication number: 20210390946
    Abstract: A speech processing method, performed by an electronic device, includes determining a first speech feature and a first text bottleneck feature based on to-be-processed speech information, determining a first combined feature vector based on the first speech feature and the first text bottleneck feature, inputting the first combined feature vector to a trained unidirectional long short-term memory (LSTM) model, performing speech processing on the first combined feature vector to obtain speech information after noise reduction, and transmitting the obtained speech information after noise reduction to another electronic device for playing.
    Type: Application
    Filed: August 30, 2021
    Publication date: December 16, 2021
    Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Yan Nan WANG, Jun HUANG
  • Patent number: 11201090
    Abstract: A method for fabricating a semiconductor structure includes forming fin structures on a base substrate; and forming dummy gate structures and first initial isolation structures. Along the extension direction of the dummy gate structures, both sides of each first initial isolation structure are in contact with a dummy gate structure. The method includes forming a first dielectric layer on the base substrate, the top and sidewall surfaces of the fin structures, and the sidewall surfaces of the dummy gate structures and the first initial isolation structure; removing the dummy gate structures to form dummy gate openings; and removing a portion of each first initial isolation structure along the width direction of the fin structures to form a first isolation structure. Along the width direction of the fin structures, the first isolation structure has a top dimension smaller than a bottom dimension. The method further includes forming gate structures.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: December 14, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 11189538
    Abstract: The present disclosure provides a method that includes providing an integrated circuit (IC) substrate having various devices and an interconnection structure that couples the devices to an integrated circuit; forming a first passivation layer on the IC substrate; forming a redistribution layer on the first passivation layer, the redistribution layer being electrically connected to the interconnection structure; forming a second passivation layer on the redistribution layer and the first passivation layer; forming a polyimide layer on the second passivation layer; patterning the polyimide layer, resulting in a polyimide opening in the polyimide layer; and etching the second passivation layer through the polyimide opening using the polyimide layer as an etch mask.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Mao-Nan Wang, Kuo-Chin Chang, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 11182464
    Abstract: A system and method are described for performing authentication on a computing device using a mobile device connected over an audio channel to the computing device, in scenarios where smart card authentication may have been traditionally used. An application executing on the computing device receives a request from a user, which request requires authentication of the user before being allowed by the application. An audio transmission containing encoded data including information authenticating the user is received at the computing device from the user's mobile device via a microphone. The audio transmission is decoded and the information authenticating the user is extracted. The information authenticating the user is verified and the request is allowed in the application.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: November 23, 2021
    Assignee: VMware, Inc.
    Inventors: Sam Zhao, Shengbo Teng, Nan Wang, Bomin Nie
  • Publication number: 20210356544
    Abstract: A method of performing multidimensional magnetic resonance imaging on a subject comprises collecting imaging data for a region of interest of the subject, the imaging data related to one or more spatially-varying parameters of the subject within the region of interest; collecting auxiliary data for the region of interest in the subject, the auxiliary data related to one or more time-varying parameters of the subject within the region of interest; linking the imaging data and the auxiliary data; and constructing an image tensor with one or more temporal dimensions based on at least a portion of the linked imaging data and at least a portion of the linked auxiliary data.
    Type: Application
    Filed: May 28, 2021
    Publication date: November 18, 2021
    Inventors: Debiao Li, Anthony Christodoulou, Zhaoyang Fan, Zixin Deng, Nan Wang, Zhengwei Zhou, Sen Ma, Christopher Nguyen, Yibin Xie, Jaime Shaw
  • Publication number: 20210359126
    Abstract: A semiconductor structure and its fabrication method are provided. The method includes: providing a substrate; forming an isolation structure on the substrate; forming a gate structure on the isolation structure; forming a first opening in the gate structure; and forming a first conductive structure in the first opening. Sidewall surfaces of the first conductive structure are in contact with a gate electrode layer of the gate structure.
    Type: Application
    Filed: April 13, 2021
    Publication date: November 18, 2021
    Inventor: Nan WANG
  • Publication number: 20210350170
    Abstract: Related are a localization method and apparatus based on a shared map, an electronic device and a storage medium. The method includes that: from global map data, including at least one key frame, of an image collected by a first terminal, local map data associated with the key frame are extracted; a present frame in an image collected by a second terminal is acquired; and feature matching is performed on the present frame and the local map data, and a localization result for the present frame is obtained according to a matching result. With the adoption of the present disclosure, multiple moving terminals can be accurately localized to each other in the shared map.
    Type: Application
    Filed: July 23, 2021
    Publication date: November 11, 2021
    Inventors: Weijian Xie, Nan Wang, Quanhao Qian, Guofeng Zhang
  • Publication number: 20210347667
    Abstract: A process for co-depositing tailings streams and/or tailings products is provided comprising providing a tailings containment structure; and co-depositing at least two different tailings streams and/or tailings products into the tailings containment structure.
    Type: Application
    Filed: May 5, 2020
    Publication date: November 11, 2021
    Inventors: ADEDEJI DUNMOLA, ERIC LeNEVE, JONATHAN SPENCE, ROBERTINO HERTANTO, NAN WANG, RANDY MIKULA, JAMES LORENTZ, PETER READ
  • Patent number: 11171062
    Abstract: A semiconductor structure and a method for forming same, the forming method including: providing a base, where the base includes a substrate and a fin protruding from the substrate, an isolation layer is formed on the substrate exposed by the fin, and the isolation layer covers a part of side walls of the fin; forming a dummy gate structure across the fin, including a dummy gate layer, where the dummy gate structure covers a part of the top and a part of the side walls of the fin; forming an interlayer dielectric layer on the substrate exposed by the dummy gate structure, where the interlayer dielectric layer exposes the top of the dummy gate structure; removing the dummy gate layer and forming an opening in the interlayer dielectric layer; removing partial thickness of the isolation layer exposed by the opening and forming a groove in the isolation layer; and forming a gate structure in the groove and the opening, where the gate structure crosses the fin and covers a part of the top and a part of the side wa
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: November 9, 2021
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Nan Wang, Zhan Ying
  • Patent number: 11171278
    Abstract: A thermoelectric conversion material having a high dimensionless figure of merit ZT includes: a large number of polycrystalline grains which include a skutterudite-type crystal structure containing Yb, Co, and Sb; and an intergranular layer which is between the neighboring polycrystalline grains and includes crystals in which an atomic ratio of O to Yb is more than 0.4 and less than 1.5. A method for manufacturing a thermoelectric conversion material includes: a weighing step; a mixing step; a ribbon preparation step by rapidly cooling and solidifying a melt of the raw materials by using a rapid liquid cooling solidifying method; a first heat treatment step including heat treating in an inert atmosphere with an adjusted oxygen concentration; a second heat treatment step including heat treating in a reducing atmosphere; and manufacturing the thermoelectric conversion material by a pressure sintering step in an inert atmosphere.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: November 9, 2021
    Assignee: HITACHI METALS, LTD.
    Inventors: Takeshi Shimada, Nan Wang, Michiko Matsuda
  • Publication number: 20210332443
    Abstract: A molecular marker for the selection and breeding of fine-wool sheep is disclosed. The marker is an STR marker comprising a (CA)n repeat core sequence, with n between 5 and 24 that can be obtained by PCR amplification of genomic DNA of sheep using the primers shown in SEQ ID NO: 1 and SEQ ID NO: 2 and sequencing the PCR product. When n is 17 or 18, a sheep is a fine-wool breed, and when n is 23 or 24, a sheep is a non-fine-wool breed. When the CA repeat is discontinuous, i.e., divided into two segments (e.g., 12+11 or 13+11) separated by two bases TA or GA, a sheep is a hybrid breed of fine-wool sheep and non-fine-wool sheep. Use of the marker provides methods of identifying of fine-wool sheep breeds, and efficient and accurate selection of fine-wool sheep or the hybrid offspring of fine-wool sheep for breeding.
    Type: Application
    Filed: September 2, 2020
    Publication date: October 28, 2021
    Applicant: China Jiliang University
    Inventors: Feng Guan, Xinyu Hu, Nan Wang, Yuting Jin, Guoqing Shi, Pengcheng Wan, Rong Dai, Aichun Xu, Jian Ge, Jun Liu
  • Publication number: 20210335671
    Abstract: A fabrication method of a semiconductor structure is provided. The method includes: providing a substrate; forming fin structures on the substrate along a first direction with isolation grooves between adjacent fin structures, where each fin structure includes sacrificial layers stacked along a normal direction of the substrate and a channel layer between every two adjacent sacrificial layers; forming a first isolation layer in each isolation groove; forming a second isolation layer at a surface of each first isolation layer to fill up a corresponding isolation groove; forming a dummy gate structure; removing first isolation layers; removing the dummy gate structure to form a gate opening at ends of the sacrificial layers along a second direction perpendicular to the first direction; removing the sacrificial layers to form gate grooves between adjacent channel layers; and forming a gate structure in the gate opening and the gate grooves surrounding the channel layers.
    Type: Application
    Filed: April 7, 2021
    Publication date: October 28, 2021
    Inventor: Nan WANG
  • Publication number: 20210335704
    Abstract: A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a substrate; a gate structure on the substrate and extending along a first direction; source/drain doped layers in the substrate at sides of the gate structure; a first conductive structure on the source/drain doped layers; an opening at a top of the gate structure and the first conductive structure; and a second conductive structure in the opening. The opening extends along a second direction and the second direction is different from the first direction. The second conductive structure is insulated from the first conductive structure and in contact with the gate structure.
    Type: Application
    Filed: April 2, 2021
    Publication date: October 28, 2021
    Inventor: Nan WANG
  • Patent number: 11158532
    Abstract: The present disclosure provides a semiconductor device and a fabrication method. The method includes: providing a substrate and forming initial fins on the substrate. The initial fins include a sacrificial material layer and a first material layer on the sacrificial material layer, first trenches are formed between adjacent initial fins, and the first trenches expose the substrate. A first layer is formed in the first trenches. Second trenches are formed in the initial fins. The second trenches expose the substrate, the sacrificial material layer is formed into a sacrificial fin layer, the first material layer is formed into fins, and the fins are located on the sacrificial fin layer. The sacrificial fin layer is removed to form first fin openings between the substrate and the fins. An isolation structure is formed on the substrate and in the first fin openings.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: October 26, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang