Patents by Inventor Nan Wang

Nan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11302584
    Abstract: A semiconductor structure includes: a base substrate; two first fin structures formed on the base substrate; an isolation structure formed on the base substrate, wherein a top surface of the isolation structure is lower than top surfaces of the two first fin structures, the isolation structure covers a portion of sidewall surfaces of the two first fin structures, the isolation structure includes a first region, located between the two first fin structures, and two second regions, and the top surface of the isolation structure formed in the first region adjacent to the two first fin structures is higher than the top surface of the isolation structure formed in the two second regions; and a plurality of source/drain openings formed in the first fin structures and having a bottom surface lower than the top surface of the isolation structure formed in the two second regions.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: April 12, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 11301641
    Abstract: A terminal for generating music may identify, based on execution of scenario recognition, scenarios for images previously received by the terminal. The terminal may generate respective description texts for the scenarios. The terminal may execute keyword-based rhyme matching based on the respective description texts. The terminal may generate respective rhyming lyrics corresponding to the images. The terminal may convert the respective rhyming lyrics corresponding to the images into a speech. The terminal may synthesize the speech with preset background music to obtain image music.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: April 12, 2022
    Assignee: Tencent Technology (Shenzhen) Company Limited
    Inventors: Nan Wang, Wei Liu, Lin Ma, Wenhao Jiang, Guangzhi Li, Shiyin Kang, Deyi Tuo, Xiaolong Zhu, Youyi Zhang, Shaobin Lin, Yongsen Zheng, Zixin Zou, Jing He, Zaizhen Chen, Pinyi Li
  • Publication number: 20220095481
    Abstract: A computing system includes a liquid cooled segment and an air cooled segment that are both removably received and secured inside a chassis with a fixed physical arrangement relative to one another. The fluid cooled segment includes an enclosure forming an enclosed space for placement of one or more high heat generating components. The enclosed space being in fluid communication with an inlet tube for receiving a cooling fluid and an outlet tube for expelling the cooling fluid that has been used to cool the high heat generating components. The enclosure includes a leak proof connector configured on the enclosure. The air cooled segment includes one or more reduced heat generating components. The reduced heat generating components are electrically coupled to the high heat generating components through the leak proof connector.
    Type: Application
    Filed: October 1, 2020
    Publication date: March 24, 2022
    Applicant: Dell Products, L.P.
    Inventors: Xin Zhi Ma, Nan Wang
  • Patent number: 11281632
    Abstract: An object information processing method includes obtaining an information creation request. The information creation request carries a first address identifier of a target object. The target object includes a subdirectory or a sub-file. The method further includes determining a second address identifier of a parent directory to which the target object belongs according to the first address identifier, searching for an information storage area storing metadata of the parent directory according to the second address identifier, and performing data updating for the information storage area according to the first address identifier to create an association relationship between the parent directory and the target object in the metadata.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: March 22, 2022
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Nan Wang, Zheng Chen, Jinming Liu, Hongwen Huang, Xiaoqian Zhan
  • Publication number: 20220086149
    Abstract: Techniques for storage management involve: receiving, at a storage server, an access request for target data from a client, wherein the access request occurs in a session between the storage server and the client; determining, based on attribute information of the client, security information of the session, wherein the security information indicates whether the session is subjected to antivirus protection; and executing, based on the security information, an access operation specified by the access request on the target data. Therefore, the performance of the storage server can be improved while the security of the storage server is ensured.
    Type: Application
    Filed: January 27, 2021
    Publication date: March 17, 2022
    Inventors: Ying Yu, Jing Li, Ming Yue, Jia Huang, Nan Wang
  • Publication number: 20220084249
    Abstract: Collecting time of collecting a first image frame to be processed is acquired. Calibrated time of the first image frame is acquired by correcting the collecting time of the first image frame according to currently calibrated time offset information for the first image frame. A current location is determined based on the first image frame and inertial sensor information acquired at the calibrated time of the first image frame.
    Type: Application
    Filed: November 29, 2021
    Publication date: March 17, 2022
    Inventors: Danpeng CHEN, Nan WANG, Bangbang YANG, Guofeng ZHANG
  • Publication number: 20220077304
    Abstract: Semiconductor device and fabrication method are provided by providing initial fins discretely arranged on a substrate; forming an isolation structure on the substrate; forming a connecting layer on sidewalk of the initial fins and between adjacent initial fins; forming a dummy gate structure across the initial fins and the connecting layer on the substrate, covering sidewalk of the connecting layer and a portion of a top surface of the initial fins; forming grooves in the initial fins on both sides of the dummy gate structure, and forming source and drain doped layers in the grooves; forming a dielectric layer on the substrate, covering sidewalls of the dummy gate structure and the source and drain doped layers, that a top surface of the dielectric layer is flush with a top surface of the dummy gate structure; and removing the dummy gate structure to form a gate structure.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 10, 2022
    Inventor: Nan WANG
  • Publication number: 20220072825
    Abstract: Heat sink and method of manufacturing a graphene based heat sink, the method comprising: providing a first and second graphene film; arranging a layer of nanoparticles on a surface of the first and second graphene film to improve an adhesion strength between the graphene films; attaching the second graphene film to the first graphene film by means of an adhesive and the layer of nanoparticles; forming a laminated graphene film comprising a number of graphene film layers by repeating the steps, wherein the laminated graphene film is formed to have an anisotropic thermal conductivity; assembling a plurality of laminated graphene films by applying pressure and heat to cure the adhesive to form a graphene block; and removing selected portions of the graphene block to form a heat sink comprising fins extending from a base plate of the heat sink.
    Type: Application
    Filed: November 12, 2021
    Publication date: March 10, 2022
    Applicant: SHT Smart High-Tech AB
    Inventors: Johan LIU, Nan WANG
  • Patent number: 11271001
    Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate having a first region, a second region and a third region; forming a dielectric layer on the base substrate; forming a first mask layer on the dielectric layer in the second region; forming a second mask layer on sidewall surfaces of the first mask layer and on the dielectric layer in the second region; etching the dielectric layer in the first region and the third region using the first mask layer and the second mask layer as an etching mask to form a first trench in the first region and a first trench in the third region; removing the first mask; and etching the dielectric layer in the second region using the second mask layer as an etching mask to form a second trench in the dielectric layer in the second region.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: March 8, 2022
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Nan Wang
  • Publication number: 20220052892
    Abstract: In one example aspect, a method is provided of preparing a symbol for transmission, the method comprising applying a window function to a symbol to generate a modified symbol, wherein a property of the window function is based on a channel length of a transmission channel over which the modified symbol is to be transmitted, and causing the modified symbol to be transmitted over the transmission channel.
    Type: Application
    Filed: December 21, 2018
    Publication date: February 17, 2022
    Inventors: Ang Feng, Tao Huang, Jinlai He, Nan Wang, Dong Wang, Guozhu Li
  • Publication number: 20220049960
    Abstract: A method for aligning coordinate systems includes: in response to that a second terminal triggers alignment of the coordinate systems, obtaining, by the second terminal, map information stored in a cloud or obtaining, by the second terminal, the map information from a first terminal; and transforming, by the second terminal, a second coordinate system of the second terminal into an initial coordinate system corresponding to the map information stored in the cloud or obtained from the first terminal, or transforming, by the second terminal, the initial coordinate system corresponding to the map information stored in the cloud or obtained from the first terminal into the second coordinate system of the second terminal; herein the initial coordinate system is used for defining a positional relationship between the first terminal and the second terminal when the map information is in a sharing state.
    Type: Application
    Filed: October 29, 2021
    Publication date: February 17, 2022
    Applicant: Zhejiang SenseTime Technology Development Co., Ltd.
    Inventors: Weijian XIE, Quanhao QIAN, Nan WANG, Guofeng ZHANG
  • Patent number: 11250035
    Abstract: A knowledge graph generating apparatus, method and non-transitory computer readable storage medium thereof are provided. The apparatus marks an entity-relationship of the template of goods information in the template of webpage according to the operating signal and generates an extraction rule set, wherein the template of webpage is one of multiple goods webpages and has a template format. The apparatus extracts a plurality of first product information of the first goods webpages according to the extraction rule set, wherein the first goods webpages have the template format and are selected from the goods webpages. The apparatus generates a classified goods information result through a product information classification model, wherein the product information classification model is generated based on the first product information and the entity-relationship of the template of goods information.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: February 15, 2022
    Assignee: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Hsin-Yi Kuo, You-Cyuan Yang, Wen-Fa Huang, Wen-Nan Wang, Ping-I Chen
  • Publication number: 20220037338
    Abstract: A semiconductor structure and a forming method thereof are provided.
    Type: Application
    Filed: November 25, 2020
    Publication date: February 3, 2022
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan WANG
  • Patent number: 11235557
    Abstract: Heat sink and method of manufacturing a graphene based heat sink, the method comprising: providing a first and second graphene film; arranging a layer of nanoparticles on a surface of the first and second graphene film to improve an adhesion strength between the graphene films; attaching the second graphene film to the first graphene film by means of an adhesive and the layer of nanoparticles; forming a laminated graphene film comprising a number of graphene film layers by repeating the steps, wherein the laminated graphene film is formed to have an anisotropic thermal conductivity; assembling a plurality of laminated graphene films by applying pressure and heat to cure the adhesive to form a graphene block; and removing selected portions of the graphene block to form a heat sink comprising fins extending from a base plate of the heat sink.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: February 1, 2022
    Assignee: SHT Smart High-Tech AB
    Inventors: Johan Liu, Nan Wang
  • Publication number: 20220028988
    Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate; a gate structure on the base substrate; source/drain doped layers in the base substrate on sides of the gate structure; a first dielectric layer on the base substrate and covering the source/drain doped layers; a mask layer on a top of the gate structure between the source/drain doped layers; a second dielectric layer on the first dielectric layer and exposing a surface of the mask layer; first grooves in the second dielectric layer and the first dielectric layer, and exposing the source/drain doped layers; a first conductive structure in each first groove; a second groove in the mask layer, and exposing the gate structure at a bottom of the second groove; and a spacer on sidewalls of the second groove.
    Type: Application
    Filed: October 7, 2021
    Publication date: January 27, 2022
    Inventor: Nan WANG
  • Publication number: 20220028990
    Abstract: A semiconductor structure and a method for forming the same are provided. One form of a forming method includes: providing a base, the base including a device region and a dummy device region, the base including an isolation layer, gate structures located on the isolation layer, a first mask layer located on the gate structures, a source-drain plug located between the gate structures and on the isolation layer, and a second mask layer located on the source-drain plug. In implementations of the present disclosure, the first mask layer and the second mask layer on the dummy device region are separately removed. Correspondingly, the first opening and the second opening respectively expose the gate structures and the source-drain plug in the dummy device region. The gate structures exposed by the first opening and the source-drain plug exposed by the second opening are removed in the same step.
    Type: Application
    Filed: November 25, 2020
    Publication date: January 27, 2022
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan WANG
  • Patent number: 11233054
    Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate, which includes a first region, a second region, and a third region. The semiconductor structure also includes a first fin, a second fin, and a third fin formed on the first, second, and third regions, respectively. Moreover, the semiconductor structure includes an isolation layer formed on the substrate, and a portion of sidewall surface of each of the first, second, and third fins. In addition, the semiconductor structure includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer formed on the first, second, and third fins, respectively. Two sides of the third epitaxial layer are in contact with the first epitaxial layer and the second epitaxial layer, respectively. Further, the semiconductor structure includes a conductive structure formed on the first, second, and third epitaxial layers.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: January 25, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 11222857
    Abstract: In some embodiments, the present disclosure relates to a method including forming an interconnect structure over a substrate. A bond pad may be coupled to the interconnect structure, and a polymeric material may be deposited over the bond pad. In some embodiments, the method further includes performing a patterning process to remove a portion of the polymeric material to form an opening in the polymeric material. The opening directly overlies and exposes the bond pad. Further, the method includes a first cleaning process. The polymeric material is cured to form a polymeric protection layer, and a second cleaning process is performed.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: January 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Fan Huang, Dian-Hau Chen, Mao-Nan Wang, Tzu-Li Lee, Yen-Ming Chen, Tzung-Luen Li
  • Publication number: 20220005931
    Abstract: A semiconductor device and a forming method thereof are provided. The semiconductor device includes a substrate, a fin located on the substrate, and a gate structure located on the substrate and across the fin. The fin includes a first region, and the fin of the first region includes a gate groove and a channel layer located between adjacent gate grooves. The gate structure covers a sidewall and a top of the fin of the first region, fills the gate groove and surrounds the channel layer. A width of the gate structure located in the gate groove is smaller than a width of the gate structure located on the top of the fin of the first region.
    Type: Application
    Filed: May 10, 2021
    Publication date: January 6, 2022
    Inventor: Nan WANG
  • Patent number: 11217681
    Abstract: Fabrication method and semiconductor device are provided. The method includes: providing a base substrate including a first region and a second region adjacent to the first region, with first fins disposed on the base substrate in the first region and on the base substrate in the second region, and initial openings disposed between adjacent first fins; forming sidewall spacers on sidewalls of the first fins to form openings from the initial openings; and forming the second fins in the openings of the second region.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: January 4, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang