Abstract: Collecting time of collecting a first image frame to be processed is acquired. Calibrated time of the first image frame is acquired by correcting the collecting time of the first image frame according to currently calibrated time offset information for the first image frame. A current location is determined based on the first image frame and inertial sensor information acquired at the calibrated time of the first image frame.

Abstract: Techniques for storage management involve: receiving, at a storage server, an access request for target data from a client, wherein the access request occurs in a session between the storage server and the client; determining, based on attribute information of the client, security information of the session, wherein the security information indicates whether the session is subjected to antivirus protection; and executing, based on the security information, an access operation specified by the access request on the target data. Therefore, the performance of the storage server can be improved while the security of the storage server is ensured.

Abstract: Semiconductor device and fabrication method are provided by providing initial fins discretely arranged on a substrate; forming an isolation structure on the substrate; forming a connecting layer on sidewalk of the initial fins and between adjacent initial fins; forming a dummy gate structure across the initial fins and the connecting layer on the substrate, covering sidewalk of the connecting layer and a portion of a top surface of the initial fins; forming grooves in the initial fins on both sides of the dummy gate structure, and forming source and drain doped layers in the grooves; forming a dielectric layer on the substrate, covering sidewalls of the dummy gate structure and the source and drain doped layers, that a top surface of the dielectric layer is flush with a top surface of the dummy gate structure; and removing the dummy gate structure to form a gate structure.

Abstract: Heat sink and method of manufacturing a graphene based heat sink, the method comprising: providing a first and second graphene film; arranging a layer of nanoparticles on a surface of the first and second graphene film to improve an adhesion strength between the graphene films; attaching the second graphene film to the first graphene film by means of an adhesive and the layer of nanoparticles; forming a laminated graphene film comprising a number of graphene film layers by repeating the steps, wherein the laminated graphene film is formed to have an anisotropic thermal conductivity; assembling a plurality of laminated graphene films by applying pressure and heat to cure the adhesive to form a graphene block; and removing selected portions of the graphene block to form a heat sink comprising fins extending from a base plate of the heat sink.

Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate having a first region, a second region and a third region; forming a dielectric layer on the base substrate; forming a first mask layer on the dielectric layer in the second region; forming a second mask layer on sidewall surfaces of the first mask layer and on the dielectric layer in the second region; etching the dielectric layer in the first region and the third region using the first mask layer and the second mask layer as an etching mask to form a first trench in the first region and a first trench in the third region; removing the first mask; and etching the dielectric layer in the second region using the second mask layer as an etching mask to form a second trench in the dielectric layer in the second region.

Abstract: A method for aligning coordinate systems includes: in response to that a second terminal triggers alignment of the coordinate systems, obtaining, by the second terminal, map information stored in a cloud or obtaining, by the second terminal, the map information from a first terminal; and transforming, by the second terminal, a second coordinate system of the second terminal into an initial coordinate system corresponding to the map information stored in the cloud or obtained from the first terminal, or transforming, by the second terminal, the initial coordinate system corresponding to the map information stored in the cloud or obtained from the first terminal into the second coordinate system of the second terminal; herein the initial coordinate system is used for defining a positional relationship between the first terminal and the second terminal when the map information is in a sharing state.

Abstract: In one example aspect, a method is provided of preparing a symbol for transmission, the method comprising applying a window function to a symbol to generate a modified symbol, wherein a property of the window function is based on a channel length of a transmission channel over which the modified symbol is to be transmitted, and causing the modified symbol to be transmitted over the transmission channel.

Abstract: A knowledge graph generating apparatus, method and non-transitory computer readable storage medium thereof are provided. The apparatus marks an entity-relationship of the template of goods information in the template of webpage according to the operating signal and generates an extraction rule set, wherein the template of webpage is one of multiple goods webpages and has a template format. The apparatus extracts a plurality of first product information of the first goods webpages according to the extraction rule set, wherein the first goods webpages have the template format and are selected from the goods webpages. The apparatus generates a classified goods information result through a product information classification model, wherein the product information classification model is generated based on the first product information and the entity-relationship of the template of goods information.

Abstract: A semiconductor structure and a forming method thereof are provided.

Abstract: Heat sink and method of manufacturing a graphene based heat sink, the method comprising: providing a first and second graphene film; arranging a layer of nanoparticles on a surface of the first and second graphene film to improve an adhesion strength between the graphene films; attaching the second graphene film to the first graphene film by means of an adhesive and the layer of nanoparticles; forming a laminated graphene film comprising a number of graphene film layers by repeating the steps, wherein the laminated graphene film is formed to have an anisotropic thermal conductivity; assembling a plurality of laminated graphene films by applying pressure and heat to cure the adhesive to form a graphene block; and removing selected portions of the graphene block to form a heat sink comprising fins extending from a base plate of the heat sink.

Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate; a gate structure on the base substrate; source/drain doped layers in the base substrate on sides of the gate structure; a first dielectric layer on the base substrate and covering the source/drain doped layers; a mask layer on a top of the gate structure between the source/drain doped layers; a second dielectric layer on the first dielectric layer and exposing a surface of the mask layer; first grooves in the second dielectric layer and the first dielectric layer, and exposing the source/drain doped layers; a first conductive structure in each first groove; a second groove in the mask layer, and exposing the gate structure at a bottom of the second groove; and a spacer on sidewalls of the second groove.

Abstract: A semiconductor structure and a method for forming the same are provided. One form of a forming method includes: providing a base, the base including a device region and a dummy device region, the base including an isolation layer, gate structures located on the isolation layer, a first mask layer located on the gate structures, a source-drain plug located between the gate structures and on the isolation layer, and a second mask layer located on the source-drain plug. In implementations of the present disclosure, the first mask layer and the second mask layer on the dummy device region are separately removed. Correspondingly, the first opening and the second opening respectively expose the gate structures and the source-drain plug in the dummy device region. The gate structures exposed by the first opening and the source-drain plug exposed by the second opening are removed in the same step.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate, which includes a first region, a second region, and a third region. The semiconductor structure also includes a first fin, a second fin, and a third fin formed on the first, second, and third regions, respectively. Moreover, the semiconductor structure includes an isolation layer formed on the substrate, and a portion of sidewall surface of each of the first, second, and third fins. In addition, the semiconductor structure includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer formed on the first, second, and third fins, respectively. Two sides of the third epitaxial layer are in contact with the first epitaxial layer and the second epitaxial layer, respectively. Further, the semiconductor structure includes a conductive structure formed on the first, second, and third epitaxial layers.

Abstract: In some embodiments, the present disclosure relates to a method including forming an interconnect structure over a substrate. A bond pad may be coupled to the interconnect structure, and a polymeric material may be deposited over the bond pad. In some embodiments, the method further includes performing a patterning process to remove a portion of the polymeric material to form an opening in the polymeric material. The opening directly overlies and exposes the bond pad. Further, the method includes a first cleaning process. The polymeric material is cured to form a polymeric protection layer, and a second cleaning process is performed.

Abstract: A semiconductor device and a forming method thereof are provided. The semiconductor device includes a substrate, a fin located on the substrate, and a gate structure located on the substrate and across the fin. The fin includes a first region, and the fin of the first region includes a gate groove and a channel layer located between adjacent gate grooves. The gate structure covers a sidewall and a top of the fin of the first region, fills the gate groove and surrounds the channel layer. A width of the gate structure located in the gate groove is smaller than a width of the gate structure located on the top of the fin of the first region.

Abstract: Fabrication method and semiconductor device are provided. The method includes: providing a base substrate including a first region and a second region adjacent to the first region, with first fins disposed on the base substrate in the first region and on the base substrate in the second region, and initial openings disposed between adjacent first fins; forming sidewall spacers on sidewalls of the first fins to form openings from the initial openings; and forming the second fins in the openings of the second region.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, including a plurality of protrusions; a plurality of fins formed over the substrate and aligned with the plurality of protrusions; and an isolation structure formed on the substrate and between the protrusions and the fins. An orthographic projection of each of the plurality of fins and an orthographic projection of a corresponding protrusion of the plurality of protrusions on the substrate coincide with each other.

Abstract: A semiconductor device and a fabrication method are provided. The semiconductor device includes: a base substrate; a gate structure on the base substrate including a first portion in a first region and a second portion in a second region; and a separation section in the first portion of the gate structure in the first region. A length of the first portion of the gate structure in the first region is larger than a length of the second portion of the gate structure in the second region. A top surface of the separation section is higher than a top surface of the gate structure.

Abstract: A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a base substrate; a gate structure on the base substrate, including a first portion in a first region and a second portion in a second region; and one or more stop layers on the base substrate and located in the first portion of the gate structure in the first region. A length of the first portion of the gate structure in the first region is larger than a length of the second portion of the gate structure in the second region.

Abstract: A semiconductor device and fabrication method thereof are provided. The method includes: providing a gate structure, a first dielectric layer, and source/drain doped layers on a base substrate and in the base substrate on sides of the gate structure; forming a mask layer on the gate structure between the source/drain doped layers; forming a second dielectric layer on the first dielectric layer and exposing the mask layer; etching the second dielectric layer and the first dielectric layer using the mask layer as an etch mask, to form first grooves on the sides of the gate structure and exposing the source/drain doped layers; forming a first conductive structure in each first groove; patterning the mask layer to form a second groove in the mask layer to expose the gate structure at the bottom of the second groove; and forming a spacer on sidewalls of the second groove.