Abstract: A semiconductor device and a method for forming the semiconductor device are provided. The method includes providing a substrate; forming a fin on the substrate, where the substrate includes a fin dense region and a fin sparse region; forming a gate structure across the fin over the substrate; forming a source-drain doped layer in the fin on both sides of the gate structure; forming a dielectric layer over the substrate, where the dielectric layer covers a top of the gate structure; and forming a first through-hole in the dielectric layer on a side of the gate structure in the fin sparse region, where a bottom of the first through-hole exposes a top sidewall of the gate structure.

Abstract: A semiconductor device and a method for forming the semiconductor device are provided. The method includes providing a substrate including an NMOS region and a PMOS region, forming an isolation layer on the substrate, forming initial hard mask layers on the isolation layer, and forming hard mask layers by removing a number of initial hard mask layers from the initial hard mask layers. The method also includes forming openings in the isolation layer in the NMOS region by removing portions of the isolation layer covered by the hard mask layers in the NMOS region, forming first fins in the openings in the isolation layer in the NMOS region, forming openings in the isolation layer in the PMOS region by removing portions of the isolation layer covered by the hard mask layers in the PMOS region, and forming second fins in the openings in the isolation layer in the PMOS region.

Abstract: This method is for manufacturing a thermoelectric conversion module in which a first conductive member, a thermoelectric conversion element, a second conductive member are joined by joining members, the method comprising: a step for, after applying on the first conductive member a first paste including metal particles, disposing the thermoelectric conversion element on the first paste, and compressing and spreading the first paste; a step for disposing the second conductive member, after applying a second paste including metal particles in a controlled amount, on the thermoelectric conversion element, and compressing and spreading the second paste; and a step for sintering the first and the second pastes to obtain joining members.

Abstract: A semiconductor structure and a forming method thereof are provided.

Abstract: A fabrication method of a semiconductor structure is provided. The method includes: providing a substrate; forming fin structures on the substrate along a first direction with isolation grooves between adjacent fin structures, where each fin structure includes sacrificial layers stacked along a normal direction of the substrate and a channel layer between every two adjacent sacrificial layers; forming a first isolation layer in each isolation groove; forming a second isolation layer at a surface of each first isolation layer to fill up a corresponding isolation groove; forming a dummy gate structure; removing first isolation layers; removing the dummy gate structure to form a gate opening at ends of the sacrificial layers along a second direction perpendicular to the first direction; removing the sacrificial layers to form gate grooves between adjacent channel layers; and forming a gate structure in the gate opening and the gate grooves surrounding the channel layers.

Abstract: A semiconductor structure and a formation method thereof are provided. In one form, the method includes: providing a base; patterning the base to form a substrate and discrete fins and pseudo fins which protrude from the substrate, wherein the fins are located in a device region, and the pseudo fins are located in isolation regions; removing the pseudo fins in the isolation regions; forming isolation layers on the substrate exposed by the fins, wherein the isolation layers cover part of the side walls of the fins; and thinning the isolation layers in the isolation regions, wherein the remaining isolation layers in the isolation regions are regarded as target isolation layers, and the surfaces of the target isolation layers are lower than the surfaces of the isolation layers between the discrete fins.

Abstract: A portable computing device including a central processing unit (CPU) and a controller is provided. The controller is coupled between the CPU, a graphics processing unit, and a battery module. The controller determines whether to adjust performance of the CPU and the graphics processing unit according to at least one of a battery capacity, a battery power, a battery current, a battery voltage, or a battery temperature of the battery module.

Abstract: A chip structure is provided. The chip structure includes a semiconductor substrate. The chip structure includes a first dielectric layer over the semiconductor substrate. The chip structure includes a first conductive layer over the first dielectric layer. The chip structure includes a second dielectric layer over the first conductive layer and the first dielectric layer. The chip structure includes a first conductive via passing through the second dielectric layer, the first conductive layer, and the first dielectric layer and electrically connected to the first conductive layer. The chip structure includes a second conductive via passing through the second dielectric layer and the first dielectric layer. The chip structure includes a first conductive pad over and in direct contact with the first conductive via. The chip structure includes a second conductive pad over and in direct contact with the second conductive via.

Abstract: Semiconductor structures is provided. The semiconductor structure includes a semiconductor substrate having at least one first region, a plurality of second regions and a plurality of third regions; at least one second fin formed on one second region of the plurality of second region; at least one third fin formed on one third region of the plurality of third regions; a first epitaxial layer formed in the at least one first fin; and a second epitaxial layer formed in the at least one second fin and the at least one third fin.

Abstract: A wafer cassette for receiving a wafer is provided. The wafer cassette includes a cassette housing, a first supporting rib and a second supporting rib. The first supporting rib is disposed in the cassette housing, wherein the first supporting rib includes a front supporting portion, a middle supporting portion and a rear supporting portion, the front supporting portion is connected to one end of the middle supporting portion, the rear supporting portion is connected to the other end of the middle supporting portion, and the front supporting portion has a front curved edge. The second supporting rib is disposed in the cassette housing. An edge portion of the wafer is supported by the first supporting rib and the second supporting rib, and the front supporting portion, the middle supporting portion and the rear supporting portion contact the wafer simultaneously.

Abstract: A double-sided and multilayer flexible printed circuit (FPC) substrate contains: a body, multiple tilted vias passing through the body, a sputtering layer, multiple conductive portions, and multiple copper circuit layers. The sputtering layer is adhered on the body and the multiple tilted vias. A respective conductive portion is formed in a respective titled via and is connected with the sputtering layer. The multiple copper circuit layers are located on a top and a bottom of the body and are connected with the sputtering layer, and the multiple copper circuit layers are connected via the multiple conductive portions.

Abstract: A first face region within a first image is determined. The first face region includes a location of a face within the first image. Based on the determined first face region within the first image, a predicted face region within a second image is determined. A first region of similarity within the predicted face region is determined. The first region of similarity has at least a predetermined degree of similarity to the first face region within the first image. Whether a second face region is present within the second image is determined. The location of the face within the second image is determined based on the first region of similarity, the determination of whether the second face region is present within the second image, and a face region selection rule.

Abstract: An Augmented Reality (AR) scene image processing method, an electronic device and a storage medium are provided. The method includes that: shooting pose data of an AR device is acquired; presentation special effect data of a virtual object corresponding to the shooting pose data in a reality scene is acquired based on the shooting pose data and position pose data of the virtual object in a three-dimensional scene model representing the reality scene; and an AR scene image is displayed through the AR device based on the presentation special effect information.

Abstract: A capability management method and apparatus, a computer device, and the like relate to permission management of a kernel object in an operating system, for example, permission management of a kernel object in a microkernel architecture. In the method, two types of information are stored in a capability node of a capability owner: information used to indicate that a capability is granting and information used to indicate a granted capability. A capability association relationship between a grantor and a grantee is established by recording the two types of information, so that capability copying is avoided in a capability granting procedure, and capability deletion is avoided in a procedure of rejecting a capability by the grantee, thereby ensuring a deterministic latency while implementing capability revocation and granting. The method may be applied to a smartphone system, an unmanned driving system, or the like.

Abstract: Provided herein is a plasma generating device for medical treatment and sanitizing purposes which comprises a control unit and a plasma generator connecting to the control unit. The plasma generator comprises a plasma tube having a first end and a second end; a first dielectric layer disposed on the inner surface of the plasma tube; a first electrode disposed on the first dielectric layer; a second dielectric layer disposed on the first electrode; a second electrode disposed on the second dielectric layer; and a plasma nozzle disposed on the bottom cover on the second end of the plasma tube.

Abstract: A method of establishing a secure communication channel from a first edge device that is in a first network zone across a secure overlay network to a second edge device that is in a second network zone, so that access to a computing device that is in the second network zone can be authenticated by an authentication service that is in the first network zone, includes the steps of establishing a first secure communication channel from the first edge device to the secure overlay network, receiving a request to join the secure overlay network along with administrator credential information and, responsive to the request, transmitting the administrator credential information to the authentication service for authentication through the first secure communication channel and the first edge device, and establishing a second secure communication channel from the second edge device to the secure overlay network if the authentication is received from the authentication service.

Abstract: A double-sided and multilayer flexible printed circuit (FPC) substrate contains: a body, multiple tilted vias passing through the body, a sputtering layer, multiple conductive portions, and multiple copper circuit layers. The sputtering layer is adhered on the body and the multiple tilted vias. A respective conductive portion is formed in a respective titled via and is connected with the sputtering layer. The multiple copper circuit layers are located on a top and a bottom of the body and are connected with the sputtering layer, and the multiple copper circuit layers are connected via the multiple conductive portions.

Abstract: Disclosed are a semiconductor structure and a forming method thereof.

Abstract: The invention relates to an environment-friendly friction material, which consists of the following components in parts by weight: 8-15 parts of a binding material, 3-8 parts of an organic fiber, 3-8 parts of an inorganic fiber, 3-8 parts of an anti-friction material, 15-25 parts of granite powder, 35-40 parts of marble powder, 6-10 parts of a modified organic filling material, 5-10 parts of an acidity or alkalinity regulating material, and 0.5-4.5 parts of a non-copper metal material, wherein the modified organic filling material consists of the following components in parts by weight: 25-50 parts of tyre powder, 15-25 parts of a shoe sole waste, 10-15 parts of a sepiolite fiber, 2-3 parts of a silane coupling agent, 2-5 parts of a cashew nut shell liquid, and 0.5-2 parts of an activator, with the shoe sole waste including 15-30% of POE and 5-15% of EPDM.