Patents by Inventor Nan Wang

Nan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210167185
    Abstract: A semiconductor device and a method for forming the semiconductor device are provided. The method includes providing a substrate, sequentially forming at least two sacrificial layers on the substrate, and forming a liner layer between any adjacent sacrificial layers of the at least two sacrificial layers. The method also includes forming a hard mask layer on a top layer of the at least two sacrificial layers, and sequentially etching the hard mask layer, the at least two sacrificial layers, the liner layer, and a portion of the substrate, thereby forming a plurality of fins that are discretely arranged on a remaining portion of the substrate. The method also includes forming a dummy gate structure across the plurality of fins on the remaining portion of the substrate, and removing a portion of the at least two sacrificial layers under the dummy gate structure, thereby forming tunnels.
    Type: Application
    Filed: September 23, 2020
    Publication date: June 3, 2021
    Inventor: Nan WANG
  • Publication number: 20210167071
    Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate; and a first gate structure and doped source/drain layers on the base substrate. The doped source/drain layers are on both sides of the first gate structure. The semiconductor device further includes a dielectric layer on a surface of the base substrate. The dielectric layer covers the doped source/drain layers, and the dielectric layer contains a first trench on the doped source/drain layer. The first trench includes a first region filled by an insulation layer and a second region filled by first conductive structure under the insulation layer. A top size of the insulation layer in the first region is larger than a bottom size of the insulation layer in the first region. A maximum size of the first conductive structure in the second region is smaller than the bottom size of the insulation layer in the first region.
    Type: Application
    Filed: February 17, 2021
    Publication date: June 3, 2021
    Inventor: Nan WANG
  • Patent number: 11022666
    Abstract: A method of performing multidimensional magnetic resonance imaging on a subject comprises collecting imaging data for a region of interest of the subject, the imaging data related to one or more spatially-varying parameters of the subject within the region of interest; collecting auxiliary data for the region of interest in the subject, the auxiliary data related to one or more time-varying parameters of the subject within the region of interest; linking the imaging data and the auxiliary data; and constructing an image tensor with one or more temporal dimensions based on at least a portion of the linked imaging data and at least a portion of the linked auxiliary data.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: June 1, 2021
    Assignee: Cedars-Sinai Medical Center
    Inventors: Debiao Li, Anthony Christodoulou, Zhaoyang Fan, Zixin Deng, Nan Wang, Zhengwei Zhou, Sen Ma, Christopher Nguyen, Yibin Xie, Jaime Shaw
  • Publication number: 20210153338
    Abstract: The invention relates to a heat spreading structure comprising: a first substrate layer; a second substrate layer; and a thermally conductive graphite film sandwiched between the first and second substrate layers, wherein the graphite film comprises a plurality of graphene layers having a turbostratic alignment between adjacent graphene layers. The invention also relates to a method for manufacturing a graphite film for a heat spreading structure.
    Type: Application
    Filed: April 3, 2018
    Publication date: May 20, 2021
    Applicant: SHT SMART HIGH-TECH AB
    Inventors: Johan LIU, Nan WANG
  • Publication number: 20210148648
    Abstract: Heat sink and method of manufacturing a graphene based heat sink, the method comprising: providing a first and second graphene film; arranging a layer of nanoparticles on a surface of the first and second graphene film to improve an adhesion strength between the graphene films; attaching the second graphene film to the first graphene film by means of an adhesive and the layer of nanoparticles; forming a laminated graphene film comprising a number of graphene film layers by repeating the steps, wherein the laminated graphene film is formed to have an anisotropic thermal conductivity; assembling a plurality of laminated graphene films by applying pressure and heat to cure the adhesive to form a graphene block; and removing selected portions of the graphene block to form a heat sink comprising fins extending from a base plate of the heat sink.
    Type: Application
    Filed: November 30, 2020
    Publication date: May 20, 2021
    Applicant: SHT Smart High-Tech AB
    Inventors: Johan LIU, Nan WANG
  • Patent number: 11011527
    Abstract: Semiconductor device, static random access memory (SRAM), and their fabrication methods are provided. The semiconductor device includes a base substrate with first fins formed in adjacent device regions. An isolation structure is formed on the base substrate having a top lower than the first fins. The isolation structure includes a first region and a second region, on opposite sidewalls of a corresponding first fin. The first region is between the adjacent first fins. The isolation structure has a top in the first region higher than that in the second region. A first doped layer is formed in the first fin having a portion in the second region. A dielectric layer is formed over the base substrate and a first contact hole is formed in the dielectric layer to expose a top of the first doped layer and a sidewall surface of the first doped layer, in the second region.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: May 18, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 11011627
    Abstract: A semiconductor structure and a method for forming same, the forming method including: providing a base, where the base includes a device region for forming devices and isolation regions located on two sides of the device region; patterning the base to form a substrate and fins protruding from the substrate; forming, on two sides of the device region, first dummy fins protruding from the substrate of the isolation region; and forming an isolation layer on the substrate exposed by the fins and the first dummy fins, where the isolation layer covers a part of side walls of the fin. In some implementations of the present disclosure, the setting of the first dummy fins improves the uniformity of pattern density in peripheral regions for each fin, which is advantageous for improving the thickness uniformity of an isolation layer in the device region, reducing the probability that the fin is bent or tilted, and improving electrical properties of the semiconductor structure.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: May 18, 2021
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventor: Nan Wang
  • Publication number: 20210142117
    Abstract: An apparatus and method for verification of information are provided. The apparatus for verification of information includes a storage and a processor, wherein the storage and the processor are electrically connected with each other. The storage stores a reference knowledge graph. The processor generates a to-be-verified knowledge graph of a to-be-verified article by a knowledge graph engine. The processor generates a verified result of the to-be-verified article by comparing the to-be-verified knowledge graph and the reference knowledge graph. The knowledge graph engine may generate the reference knowledge graph by searching and labeling a plurality of related articles according to a plurality of reference articles that have been labeled.
    Type: Application
    Filed: December 3, 2019
    Publication date: May 13, 2021
    Inventors: Ping-I CHEN, Wen-Nan WANG, Wen-Fa HUANG, Hsin-Yi KUO
  • Patent number: 11003893
    Abstract: A first face region within a first image is determined. The first face region includes a location of a face within the first image. Based on the determined first face region within the first image, a predicted face region within a second image is determined. A first region of similarity within the predicted face region is determined. The first region of similarity has at least a predetermined degree of similarity to the first face region within the first image. Whether a second face region is present within the second image is determined. The location of the face within the second image is determined based on the first region of similarity, the determination of whether the second face region is present within the second image, and a face region selection rule.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: May 11, 2021
    Assignee: Advanced New Technologies Co., Ltd.
    Inventors: Nan Wang, Zhijun Du, Yu Zhang
  • Patent number: 10999704
    Abstract: In one embodiment, a movement footprint of a user walking along a wall in the environment is determined at least in part based on a communication between a first communication device and a second communication device. The first communication device is carried by the user, and the second communication device is placed in the environment. A representation of the spatial division of the environment is generated based on the determined movement footprint. An estimated size associated with at least one reference object in the environment is determined according to the representation of the spatial division, and a reference size associated with the at least one reference object is obtained. Further, the representation of the spatial division is adjusted based on the estimated size and the reference size.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: May 4, 2021
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Nan Wang, Guifeng Song, Jianwen Yao, Bin Xu, Cheng Qian
  • Publication number: 20210125628
    Abstract: A method for audio recognition comprises: dividing audio data to be recognized to obtain a plurality of frames of audio data; calculating, based on audio variation trends among the plurality of frames and within each of the plurality of frames, a characteristic value for each frame of the audio data to be recognized; and matching the characteristic value of each frame of the audio data to be recognized with a pre-established audio characteristic value comparison table to obtain a recognition result, wherein the audio characteristic value comparison table is established based on the audio variation trends among the frames and within each of the frames of sample data.
    Type: Application
    Filed: January 6, 2021
    Publication date: April 29, 2021
    Inventors: ZHIJUN DU, NAN WANG
  • Patent number: 10991690
    Abstract: A semiconductor structure and a method for forming same are provided. The forming method includes: providing a substrate, a fin protruding from the substrate, and at least two channel laminates sequentially located on the fin, where each channel laminate includes a sacrificial layer and a channel layer; forming a gate structure across the channel laminates; forming, in the channel laminates, a groove that exposes the fin, where after the groove is formed, the fin, the channel layer adjacent to the fin, and the remaining sacrificial layer encircle a first trench, adjacent channel layers and the remaining sacrificial layer between the adjacent channel layers encircle a second trench; forming first spacers in the first trench and the second trench; and forming a source-drain doping layer in the groove.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: April 27, 2021
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventor: Nan Wang
  • Patent number: 10990144
    Abstract: A system may include a tank configured to hold a dielectric liquid, a rack located within the tank and having a plurality of bays, each bay configured to receive a corresponding device, an air pump configured to drive an air flow, at least one variable-buoyancy chamber mechanically coupled to at least one of the tank and the rack, each of the at least one variable-buoyancy chamber comprising a fluidically-sealed plenum and wherein the at least one variable-buoyancy chamber is configured to mechanically couple to a device-in-service, and a control subsystem configured to control a buoyancy of the at least one variable-buoyancy chamber in order to cause movement of the device-in-service relative to the rack.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: April 27, 2021
    Assignee: Dell Products L.P.
    Inventors: Nan Wang, Austin M. Shelnutt
  • Publication number: 20210118237
    Abstract: An Augmented Reality (AR) scene image processing method, an electronic device and a storage medium are provided. The method includes that: shooting pose data of an AR device is acquired; presentation special effect data of a virtual object corresponding to the shooting pose data in a reality scene is acquired based on the shooting pose data and position pose data of the virtual object in a three-dimensional scene model representing the reality scene; and an AR scene image is displayed through the AR device based on the presentation special effect information.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 22, 2021
    Inventors: Xinru HOU, Qing LUAN, Chongshan SHENG, Fei JIAO, Huafu OU, Shengchuan SHI, Nan WANG, Hanqing JIANG
  • Publication number: 20210118829
    Abstract: A chip structure is provided. The chip structure includes a semiconductor substrate. The chip structure includes a first dielectric layer over the semiconductor substrate. The chip structure includes a first conductive layer over the first dielectric layer. The chip structure includes a second dielectric layer over the first conductive layer and the first dielectric layer. The chip structure includes a first conductive via passing through the second dielectric layer, the first conductive layer, and the first dielectric layer and electrically connected to the first conductive layer. The chip structure includes a second conductive via passing through the second dielectric layer and the first dielectric layer. The chip structure includes a first conductive pad over and in direct contact with the first conductive via. The chip structure includes a second conductive pad over and in direct contact with the second conductive via.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Fan HUANG, Mao-Nan WANG, Hui-Chi CHEN, Dian-Hau CHEN, Yen-Ming CHEN
  • Patent number: 10971405
    Abstract: A method for fabricating a semiconductor device includes providing a base substrate, including a first region and a second region. The first region is located on each side of the second region, and a plurality of fin structures is formed in the first region and the second region. The method includes forming a first doped region and a second doped region in the first region and the second region, respectively in the plurality of fin structures. The concentration of doping ions in the first doped region is lower than that in the second doped region, and the doping ions in the first doped region and the second doped region are the same doping type. After forming the first doped region and the second doped region, the method includes forming a plurality of gate structures on the first doped region and the second doped region across the plurality of fin structures.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: April 6, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 10964823
    Abstract: A semiconductor structure and a method for forming same are provided. One form of the method includes: providing a substrate including a device unit area, where at least two fins are formed on the substrate, a channel structure layer is formed on the fins, which includes a first channel structure layer located on at least one fin, a second channel structure layer located on at least one fin, and a third channel structure layer located on at least one fin, the first channel structure layer includes multiple channel laminates, each channel laminate includes a first sacrificial layer and a first channel layer; forming a dummy gate structure across the channel structure layer; forming a source-drain doping layer on two sides of the dummy gate structure; and forming a gate structure at positions of the dummy gate structure and the first sacrificial layer.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 30, 2021
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventor: Nan Wang
  • Publication number: 20210091192
    Abstract: A semiconductor device and a method for forming the semiconductor device are provided. The method includes providing a substrate; forming a fin on the substrate, where the substrate includes a fin dense region and a fin sparse region; forming a gate structure across the fin over the substrate; forming a source-drain doped layer in the fin on both sides of the gate structure; forming a dielectric layer over the substrate, where the dielectric layer covers a top of the gate structure; and forming a first through-hole in the dielectric layer on a side of the gate structure in the fin sparse region, where a bottom of the first through-hole exposes a top sidewall of the gate structure.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 25, 2021
    Inventor: Nan WANG
  • Publication number: 20210090102
    Abstract: The embodiments of the present disclosure provide systems and methods for outbound forecasting, comprising receiving an initial distribution of priority values to each fulfillment center (FC) in each region, running a simulation, using a simulation algorithm, of the initial distribution, calculating an outbound capacity utilization value of each FC, determining a number of FCs comprising an outbound capacity utilization value that exceeds a predetermined threshold, feeding the simulation algorithm with the determined number of FCs to generate one or more additional distributions of priority values, generating a FC priority filter comprising an optimal set of priority values based on the one or more additional distributions of priority values, and modifying an allocation of a plurality of SKUs among a plurality of FCs based on the generated FC priority filter.
    Type: Application
    Filed: November 6, 2020
    Publication date: March 25, 2021
    Applicant: Coupang Corp.
    Inventors: Nan WANG, Ke MA, Christopher CARLSON, Bin GU, Shixian LI
  • Publication number: 20210089985
    Abstract: The embodiments of the present disclosure provide systems and methods for outbound forecasting, comprising receiving an initial set of solutions comprising receiving a prediction of a regional sales forecast indicative of a customer demand for each stock keeping unit (SKU) in each region, receiving a prediction of a correlation of one or more SKUs that will be combined in customer orders in each region, receiving a prediction of a size of customer orders in each region, wherein a customer order profile is simulated based on the predicted correlation and the predicted size, receiving an inventory stow model that is generated using at least one of open purchase orders or past customer orders; and, predicting a FC for managing outbound of each SKU based on the predicted regional sales forecast, the simulated customer order profile, and the inventory stow model, and modifying a database to assign the predicted FC to each corresponding SKU.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Applicant: Coupang, Corp.
    Inventors: Bin GU, Xiang LI, Nan WANG, Li HUANG, Ke MA