Patents by Inventor Naoharu Shinozaki
Naoharu Shinozaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9418742Abstract: A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.Type: GrantFiled: September 27, 2013Date of Patent: August 16, 2016Assignee: PS4 LUXCO S.A.R.L.Inventors: Naoharu Shinozaki, Masao Taguchi, Takahiro Hatada, Satoru Sugimoto, Satoshi Sakurakawa
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Patent number: 9190136Abstract: A ferroelectric memory device includes a memory array including a plurality of ferroelectric memory cells, a code generating circuit configured to multiply write data and a parity generator matrix to generate check bits, thereby producing a Hamming code having information bits and the check bits arranged therein, the information bits being the write data, and a driver circuit configured to write the Hamming code to the memory array, wherein the parity generator matrix has a plurality of rows, and a number of “1”s in each of the rows is an even number.Type: GrantFiled: September 12, 2014Date of Patent: November 17, 2015Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Tomohisa Hirayama, Keizo Morita, Naoharu Shinozaki
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Publication number: 20150098263Abstract: A ferroelectric memory device includes a memory array including a plurality of ferroelectric memory cells, a code generating circuit configured to multiply write data and a parity generator matrix to generate check bits, thereby producing a Hamming code having information bits and the check bits arranged therein, the information bits being the write data, and a driver circuit configured to write the Hamming code to the memory array, wherein the parity generator matrix has a plurality of rows, and a number of “1”s in each of the rows is an even number.Type: ApplicationFiled: September 12, 2014Publication date: April 9, 2015Inventors: Tomohisa HIRAYAMA, Keizo Morita, Naoharu Shinozaki
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Patent number: 8773885Abstract: A semiconductor device including: a first memory cell including a non-volatile first variable resistance element that stores data by varying a resistance value and a selection transistor that selects the first variable resistance element; a first memory layer provided with more than one such first memory cell arranged in a plane; a second memory cell including a non-volatile second variable resistance element that stores data by varying a resistance value and a selection diode that selects the second variable resistance element; and a second memory layer provided with more than one such second memory cell arranged in a plane; wherein more than one such second memory layer is stacked over the first memory layer.Type: GrantFiled: September 19, 2012Date of Patent: July 8, 2014Assignee: Spansion LLCInventor: Naoharu Shinozaki
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Publication number: 20140177339Abstract: A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.Type: ApplicationFiled: September 27, 2013Publication date: June 26, 2014Applicant: Elpida Memory, Inc.Inventors: Naoharu SHINOZAKI, Masao TAGUCHI, Takahiro HATADA, Satoru SUGIMOTO, Satoshi SAKURAKAWA
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Patent number: 8553459Abstract: A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.Type: GrantFiled: April 6, 2011Date of Patent: October 8, 2013Assignee: Elpida Memory, Inc.Inventors: Naoharu Shinozaki, Masao Taguchi, Takahiro Hatada, Satoru Sugimoto, Satoshi Sakurakawa
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Patent number: 8363466Abstract: At the time of reading, an unselected word line voltage is fixed to a first predetermined voltage (0 V or 3 V), and when selecting a word line, a selected word line voltage is set to a second predetermined voltage (?3.5 V or 0 V). This configuration eliminates an application of a pulsed voltage to the word line at the time of reading, making it possible to reduce an influence of read disturbance. In addition, even when a voltage in a range from a power source voltage to a ground voltage or a voltage over the power source voltage is required at the time of reading, it becomes a voltage about 1.5 times an absolute value of the power source voltage. Therefore, a voltage step-up circuit having a large number of stages is not required, and as a result, it is possible to achieve a reduced operation time with a low power consumption.Type: GrantFiled: December 22, 2010Date of Patent: January 29, 2013Assignee: Elpida Memory, Inc.Inventors: Naoharu Shinozaki, Masao Taguchi, Satoru Sugimoto
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Publication number: 20130016552Abstract: A semiconductor device including: a first memory cell including a non-volatile first variable resistance element that stores data by varying a resistance value and a selection transistor that selects the first variable resistance element; a first memory layer provided with more than one such first memory cell arranged in a plane; a second memory cell including a non-volatile second variable resistance element that stores data by varying a resistance value and a selection diode that selects the second variable resistance element; and a second memory layer provided with more than one such second memory cell arranged in a plane; wherein more than one such second memory layer is stacked over the first memory layer.Type: ApplicationFiled: September 19, 2012Publication date: January 17, 2013Inventor: Naoharu SHINOZAKI
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Patent number: 8289750Abstract: A semiconductor device including: a first memory cell including a non-volatile first variable resistance element that stores data by varying a resistance value and a selection transistor that selects the first variable resistance element; a first memory layer provided with more than one such first memory cell arranged in a plane; a second memory cell including a non-volatile second variable resistance element that stores data by varying a resistance value and a selection diode that selects the second variable resistance element; and a second memory layer provided with more than one such second memory cell arranged in a plane; wherein more than one such second memory layer is stacked over the first memory layer.Type: GrantFiled: January 12, 2011Date of Patent: October 16, 2012Assignee: Spansion LLCInventor: Naoharu Shinozaki
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Publication number: 20120014162Abstract: A semiconductor device including: a first memory cell including a non-volatile first variable resistance element that stores data by varying a resistance value and a selection transistor that selects the first variable resistance element; a first memory layer provided with more than one such first memory cell arranged in a plane; a second memory cell including a non-volatile second variable resistance element that stores data by varying a resistance value and a selection diode that selects the second variable resistance element; and a second memory layer provided with more than one such second memory cell arranged in a plane; wherein more than one such second memory layer is stacked over the first memory layer.Type: ApplicationFiled: January 12, 2011Publication date: January 19, 2012Inventor: Naoharu SHINOZAKI
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Patent number: 8085588Abstract: Systems and methods for programming data to a memory device (MD). The methods involve receiving the data at MD (100) from an external data source. MD includes a memory cell array (MCA) for storing the data including numbers in data blocks (DB) or memory cell array planes (MCAP). Each DB (122a, 122b, 122c, 122d) and MCAP (1020a, 1020b, 1020c, 1020d) includes memory addresses (Ads) corresponding to locations of respective transistor circuits (2021, 2022, . . . , 202n, . . . , 202m) within the MCA (120, 1020a, 1020b, 1020c, 1020d). Two or more of the transistor circuits have different threshold voltages (TVs) with respect to each other. The methods further involve programming the data to each DB or MCAP in accordance with a first mode. In the first mode, each number is programmed to a different MA of each DB or MCAP based at least in part on the different TVs.Type: GrantFiled: April 30, 2009Date of Patent: December 27, 2011Assignee: Spansion LLCInventors: Naoharu Shinozaki, Kenji Arai, Satoshi Sakurakawa
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Patent number: 8064264Abstract: A semiconductor device that includes: a memory cell array that includes non-volatile memory cells; an area that is contained in the memory cell array and stores area data; a first storage unit that holds data transferred from the memory cell array, and outputs the data; and a control circuit that selects between a primary reading mode for causing the first storage unit to hold the area data transferred from the memory cell array and to output the area data, and a secondary reading mode for causing the first storage unit to hold a plurality of pieces of divisional data formed by dividing the area data and transferred from the memory cell array and to output the divisional data.Type: GrantFiled: October 11, 2007Date of Patent: November 22, 2011Assignee: Spansion LLCInventors: Naoharu Shinozaki, Masao Taguchi, Akira Ogawa, Takuo Ito
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Publication number: 20110261622Abstract: A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.Type: ApplicationFiled: April 6, 2011Publication date: October 27, 2011Applicant: Elpida Memory, Inc.Inventors: Naoharu Shinozaki, Masao Taguchi, Takahiro Hatada, Satoru Sugimoto, Satoshi Sakurakawa
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Publication number: 20110157978Abstract: At the time of reading, an unselected word line voltage is fixed to a first predetermined voltage (0 V or 3 V), and when selecting a word line, a selected word line voltage is set to a second predetermined voltage (?3.5 V or 0 V). This configuration eliminates an application of a pulsed voltage to the word line at the time of reading, making it possible to reduce an influence of read disturbance. In addition, even when a voltage in a range from a power source voltage to a ground voltage or a voltage over the power source voltage is required at the time of reading, it becomes a voltage about 1.5 times an absolute value of the power source voltage. Therefore, a voltage step-up circuit having a large number of stages is not required, and as a result, it is possible to achieve a reduced operation time with a low power consumption.Type: ApplicationFiled: December 22, 2010Publication date: June 30, 2011Applicant: Elpida Memory, Inc.Inventors: Naoharu Shinozaki, Masao Taguchi, Satoru Sugimoto
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Patent number: 7969816Abstract: Systems and methods for reading data from or writing data to a memory device. The methods involve receiving a first pulse signal having a first pulse frequency at the memory device. The methods also involve generating, at the memory device, a second pulse signal using the first pulse signal. The second pulse signal is a compliment of the first pulse signal. The second pulse signal has a second pulse frequency that is equal to the first frequency. The fist pulse signal is used to control first read/write operations so that first data is output from or input to the memory device at a first data rate. The first and second pulse signals are used to control second read/write operations so that second data is output from or input to the memory device at a second data rate. The second data rate is twice the first data rate.Type: GrantFiled: August 26, 2009Date of Patent: June 28, 2011Assignee: Spansion LLCInventors: Naoharu Shinozaki, Satoshi Moue
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Publication number: 20110051529Abstract: Systems and methods for reading data from or writing data to a memory device. The methods involve receiving a first pulse signal having a first pulse frequency at the memory device. The methods also involve generating, at the memory device, a second pulse signal using the first pulse signal. The second pulse signal is a compliment of the first pulse signal. The second pulse signal has a second pulse frequency that is equal to the first frequency. The first pulse signal is used to control first read/write operations so that first data is output from or input to the memory device at a first data rate. The first and second pulse signals are used to control second read/write operations so that second data is output from or input to the memory device at a second data rate. The second data rate is twice the first data rate.Type: ApplicationFiled: August 26, 2009Publication date: March 3, 2011Applicant: Spansion LLCInventors: Naoharu Shinozaki, Satoshi Moue
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Patent number: 7894238Abstract: A semiconductor device including: a first memory cell including a non-volatile first variable resistance element that stores data by varying a resistance value and a selection transistor that selects the first variable resistance element; a first memory layer provided with more than one such first memory cell arranged in a plane; a second memory cell including a non-volatile second variable resistance element that stores data by varying a resistance value and a selection diode that selects the second variable resistance element; and a second memory layer provided with more than one such second memory cell arranged in a plane; wherein more than one such second memory layer is stacked over the first memory layer.Type: GrantFiled: October 17, 2008Date of Patent: February 22, 2011Assignee: Spansion LLCInventor: Naoharu Shinozaki
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Patent number: 7835172Abstract: The present invention provides a semiconductor device and a method for manufacturing thereof. The semiconductor device includes a data storage element which includes a variable resistance and an electrode, and a controller which selects a first mode that stores data by the resistance value of the variable resistance and a second mode that stores data by the amount of electrical charges stored in the electrode. By selectively using the data storage element in the first mode and the second mode, a plurality of storage modes can be implemented with a single data storage element. Thus, miniaturization and cost reduction of the semiconductor device can be achieved.Type: GrantFiled: October 1, 2008Date of Patent: November 16, 2010Assignee: Spansion LLCInventor: Naoharu Shinozaki
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Publication number: 20100277987Abstract: Systems and methods for programming data to a memory device (MD). The methods involve receiving the data at MD (100) from an external data source. MD includes a memory cell array (MCA) for storing the data including numbers in data blocks (DB) or memory cell array planes (MCAP). Each DB (122a, 122b, 122c, 122d) and MCAP (1020a, 1020b, 1020c, 1020d) includes memory addresses (Ads) corresponding to locations of respective transistor circuits (2021, 2022, . . . , 202n, . . . 202m) within the MCA (120, 1020a, 1020b, 1020c, 1020d). Two or more of the transistor circuits have different threshold voltages (TVs) with respect to each other. The methods further involve programming the data to each DB or MCAP in accordance with a first mode. In the first mode, each number is programmed to a different MA of each DB or MCAP based at least in part on the different TVs.Type: ApplicationFiled: April 30, 2009Publication date: November 4, 2010Inventors: Naoharu Shinozaki, Kenji Arai, Satoshi Sakurakawa
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Patent number: 7706186Abstract: A semiconductor device and a control method thereof that include a memory cell array having a plurality of nonvolatile memory cells and a control circuit. The control circuit starts a first operation of the memory cells in a part of the region of the memory cell array when a first command is input, then decides whether to temporarily suspend the first operation or to reset the first operation when a second command is input, and temporarily suspends the first operation if the control circuit decides to temporarily suspend the first operation, and terminates the first operation if the control circuit decides to reset the first operation.Type: GrantFiled: November 5, 2007Date of Patent: April 27, 2010Assignee: Spanion LLCInventor: Naoharu Shinozaki