Abstract: A semiconductor memory device has a mask signal receiving circuit which receives a data mask signal, fed from an external unit, out of synchronism and produces an asynchronous internal mask signal. The semiconductor memory device includes a function for interrupting a reading of data during a burst output in response to the data mask signal. The reading of data during the burst output is interrupted by using the internal mask signal. Therefore, the operation time can be shortened when the burst reading is interrupted by a write processing, and thereby the efficiency for using the data bus can be enhanced and the operation can be executed at higher speeds.

Abstract: Latches for amplifying data on bit lines are activated in response to the activation of first activating signals. Amplifying transistors to be operated in read operations and switching transistors to be operated in write operations receive the activation of second activating signals at their sources and are activated per sense amplifier array. Since the numbers of amplifying transistors and switching transistors to be operated decrease, power consumption during operation period is reduced. Besides, since the wiring lengths of second activating signal lines can be made small compared to conventional art, driving capacity of second sense amplifier control circuits can be reduced. As a result, power consumption of the sense amplifiers can be reduced significantly in read operations. By having smaller loads in the second activating signal lines, transmission time of the second activating signals can be shortened, and thus read operation time and write operation time can be reduced.

Abstract: In the present invention, an external power source supplied to an integrated circuit device is divided into a first external power source for the DLL circuit and a second external power source for circuits other than the DLL circuit. According to the present invention, it is arranged that power source noise generated in the second external power source cannot be transmitted to the variable delay circuit by utilizing the first external power source preferably for the variable delay circuit of the DLL circuit and even more preferably for its delay unit. Also, preferably, it is arranged that power source noise generated in the second external power source cannot be transmitted to the phase coincidence detection unit by utilizing the first power source for the phase coincidence detection unit in the phase comparison circuit of the DLL circuit.

Abstract: Latches for amplifying data on bit lines are activated in response to the activation of first activating signals. Amplifying transistors to be operated in read operations and switching transistors to be operated in write operations receive the activation of second activating signals at their sources and are activated per sense amplifier array. Since the numbers of amplifying transistors and switching transistors to be operated decrease, power consumption during operation period is reduced. Besides, since the wiring lengths of second activating signal lines can be made small compared to conventional art, driving capacity of second sense amplifier control circuits can be reduced. As a result, power consumption of the sense amplifiers can be reduced significantly in read operations. By having smaller loads in the second activating signal lines, transmission time of the second activating signals can be shortened, and thus read operation time and write operation time can be reduced.

Abstract: A plurality of sense amplifiers amplify parallel read data from memory cells, respectively. At least one of read amplifiers for amplifying the amplified read data respectively has a higher drivability than those of the rest of the read amplifiers. A connection switching circuit connects the sense amplifiers to a predetermined read amplifier according to an address. Switching the read data to one another before the amplification by the read amplifiers allows read data to be first outputted in burst read operation to be amplified by the read amplifier whose drivability is always high. In the burst read operation, a data output circuit first outputs read data corresponding to the read amplifier whose drivability is high. This enables reductions in read operation time and power consumption, even in a semiconductor memory in which the output orders of read data are changeable according to addresses or operation modes.

Abstract: Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock.

Abstract: A semiconductor integrated circuit including a semiconductor device has a command decoder unit for decoding command signals synchronously with an external clock. An internal signal whose timing precedes the timing of the command decoder unit decoding the command signals is used to reset the command decoder unit. Preferably, a signal produced by a DLL is used as the internal signal. Consequently, a margin in timing of actuating the semiconductor device is expanded.

Abstract: An address input circuit outputs an address signal from exterior as an internal address signal. A latching circuit accepts the internal address signal, and supplies the accepted signal to an internal circuit in conformity to the operating timing of the internal circuit. A redundancy judgement circuit judges whether or not the internal address signal yet to be accepted into the latching circuit is of a defect address, and outputs the judgement result as a redundancy judgement signal. A redundancy latching circuit accepts the redundancy judgement signal, and supplies the accepted signal to the internal circuit in conformity to the operating timing of the internal circuit. The use of the address signal before it is latched for redundancy judgement allows the redundancy judgement to be performed at earlier timing. Therefore, the amount of time needed for the read operation and write operation can be reduced.

Abstract: When a test instruction signal is outputted from a command decoder, a test mode decoder receives the test instruction signal and outputs a test signal. When a DQM switch circuit receives the test signal, the DQM switch circuit outputs a mask/disable signal (MASK0 or MASK1) inputted to any one of two mask/disable terminals (DQML, DQMU) as a mask/disable signal inputted from the two terminals DQML and DQMU to a write amplifier/sense buffer. Therefore, it is possible to execute a mask/disable operation for all of input and output data with one of the two mask/disable terminals.

Abstract: The semiconductor integrated circuit comprises a memory cell, a sense amplifier, input/output controlling circuit, a switch circuit which connects the sense amplifier and the input/output circuit, a reference timing signal generator, a timing controlling circuit having a delay element, and a switch controlling circuit which controls the switch circuit. The reference timing signal generator generates a reference timing signal necessary for read/write operations. The timing controlling circuit receives the reference timing signal and generates, by using the delay element thereof, at least one of either a read controlling signal or a write controlling signal whose timing shifts from the timing of the switch controlling signal by a predetermined amount of time. Therefore, the deviation between the timings of the switch controlling signal and the read controlling signal or the write controlling signal can easily be set to a predetermined value.

Abstract: A semiconductor integrated circuit including a semiconductor device has a command decoder unit for decoding command signals synchronously with an external clock. An internal signal whose timing precedes the timing of the command decoder unit decoding the command signals is used to reset the command decoder unit. Preferably, a signal produced by a DLL is used as the internal signal. Consequently, a margin in timing of actuating the semiconductor device is expanded.

Abstract: A semiconductor memory device having an internal circuit includes a command decoder which decodes input-command signals to supply decoded-command signals, an address-latch-signal-generation circuit, operating faster than the command decoder, which decodes the input-command signals to supply an address-latch signal, and a control circuit which controls the internal circuit based on the decoded-command signals. The semiconductor memory device further includes an address-input circuit which latches an address signal in response to the address-latch signal.

Abstract: The present invention provides an input circuit having small current consumption in a clock synchronization type semiconductor integrated circuit. The input circuit is activated by an activation signal to receive an input signal and an activation signal generating circuit generates the activation signal. The activation signal generating circuit activates intermittently the activation signal for a time shorter than a period of a clock signal and including a setup time and a hold time of the input signal in order to activate the input circuit. The input circuit is activated only for the limited time of one period of the clock signal and therefore current consumption can be reduced.

Abstract: A step-down circuit 10A comprises a voltage follower circuit 20A for receiving a voltage VG, to be measured, of an internal circuit, activated in response to activation of a test mode signal TM, and providing its output to an on-chip pad 16A. Although a large current flows through an output buffer circuit 22 of the voltage follower circuit 20A compared with that of an output buffer circuit 15 of a voltage control circuit 12, this large current does not flow when the signal TM is inactive. The voltage follower circuit having a comparatively large area on chip can commonly be used with a selection circuit for selecting one of nodes with voltages to be measured. In a case of SDRAM, the signal TM may be an output of the command decoder and a selection control signal may be an address signal.

Abstract: A semiconductor circuit which receives a strobe signal and a data signal includes a latch-signal-generation circuit which generates a first latch signal delayed by a first delay time relative to the strobe signal and a second latch signal inverted and delayed by a second delay time relative to the strobe signal, a control circuit which adaptively controls the latch-signal-generation circuit to adjust timings of the first and second latch signals such that the first delay time and the second delay time become substantially equal, and a latch circuit which latches the data signal at edge timings of the first and second latch signals.

Abstract: An input circuit for an integrated circuit receives an external signal and generates an amplified internal signal which has substantially equal rise and fall signal timing. That is, the rise time of a signal generated by the input circuit is substantially the same as the fall time of signal. This effect is achieved by regulating the current flowing through the input circuit. The input circuit includes a differential circuit which includes a first transistor that receives the external signal at its gate and a second transistor that receives a reference voltage at its gate. Sources of the first and second transistors are connected in common, and the differential circuit generates an internal signal in accordance with the current flowing through the first and second transistors. A current regulating circuit is connected to the differential circuit and regulates the current flowing through the differential circuit in response to the internal signal.

Abstract: A semiconductor memory device having an internal circuit includes a command decoder which decodes input-command signals to supply decoded-command signals, an address-latch-signal-generation circuit, operating faster than the command decoder, which decodes the input-command signals to supply an address-latch signal, and a control circuit which controls the internal circuit based on the decoded-command signals. The semiconductor memory device further includes an address-input circuit which latches an address signal in response to the address-latch signal.

Abstract: A semiconductor memory device has a mask signal receiving circuit which receives a data mask signal, fed from an external unit, out of synchronism and produces an asynchronous internal mask signal. The semiconductor memory device includes a function for interrupting a reading of data during a burst output in response to the data mask signal. The reading of data during the burst output is interrupted by using the internal mask signal. Therefore, the operation time can be shortened when the burst reading is interrupted by a write processing, and thereby the efficiency for using the data bus can be enhanced and the operation can be executed at higher speeds.

Abstract: In the present invention, an external power source supplied to an integrated circuit device is divided into a first external power source for the DLL circuit and a second external power source for circuits other than the DLL circuit. According to the present invention, it is arranged that power source noise generated in the second external power source cannot be transmitted to the variable delay circuit by utilizing the first external power source preferably for the variable delay circuit of the DLL circuit and even more preferably for its delay unit. Also, preferably, it is arranged that power source noise generated in the second external power source cannot be transmitted to the phase coincidence detection unit by utilizing the first power source for the phase coincidence detection unit in the phase comparison circuit of the DLL circuit.

Abstract: A semiconductor integrated circuit device includes a clock buffer circuit receiving a clock signal, a data buffer circuit receiving a data signal, an output circuit outputting the data signal from the data buffer circuit in accordance with the clock signal from the clock buffer circuit, and an adjustment circuit adjusting timings of the clock signal and the data signals.