Patents by Inventor Naoharu Shinozaki
Naoharu Shinozaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090262569Abstract: A semiconductor device including: a first memory cell including a non-volatile first variable resistance element that stores data by varying a resistance value and a selection transistor that selects the first variable resistance element; a first memory layer provided with more than one such first memory cell arranged in a plane; a second memory cell including a non-volatile second variable resistance element that stores data by varying a resistance value and a selection diode that selects the second variable resistance element; and a second memory layer provided with more than one such second memory cell arranged in a plane; wherein more than one such second memory layer is stacked over the first memory layer.Type: ApplicationFiled: October 17, 2008Publication date: October 22, 2009Inventor: Naoharu SHINOZAKI
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Publication number: 20090251945Abstract: The present invention provides a semiconductor device and a method for manufacturing thereof. The semiconductor device includes a data storage element which includes a variable resistance and an electrode, and a controller which selects a first mode that stores data by the resistance value of the variable resistance and a second mode that stores data by the amount of electrical charges stored in the electrode. By selectively using the data storage element in the first mode and the second mode, a plurality of storage modes can be implemented with a single data storage element. Thus, miniaturization and cost reduction of the semiconductor device can be achieved.Type: ApplicationFiled: October 1, 2008Publication date: October 8, 2009Inventor: Naoharu SHINOZAKI
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Patent number: 7471585Abstract: A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.Type: GrantFiled: August 24, 2006Date of Patent: December 30, 2008Assignee: Fujitsu LimitedInventors: Naoharu Shinozaki, Tatsuya Kanda, Takahiko Sato, Akihiro Funyu
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Publication number: 20080140880Abstract: A semiconductor device and a control method thereof that include a memory cell array having a plurality of nonvolatile memory cells and a control circuit. The control circuit starts a first operation of the memory cells in a part of the region of the memory cell array when a first command is input, then decides whether to temporarily suspend the first operation or to reset the first operation when a second command is input, and temporarily suspends the first operation if the control circuit decides to temporarily suspend the first operation, and terminates the first operation if the control circuit decides to reset the first operation.Type: ApplicationFiled: November 5, 2007Publication date: June 12, 2008Inventor: Naoharu Shinozaki
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Publication number: 20080098165Abstract: A semiconductor device that includes: a memory cell array that includes non-volatile memory cells; an area that is contained in the memory cell array and stores area data; a first storage unit that holds data transferred from the memory cell array, and outputs the data; and a control circuit that selects between a primary reading mode for causing the first storage unit to hold the area data transferred from the memory cell array and to output the area data, and a secondary reading mode for causing the first storage unit to hold a plurality of pieces of divisional data formed by dividing the area data and transferred from the memory cell array and to output the divisional data.Type: ApplicationFiled: October 11, 2007Publication date: April 24, 2008Inventors: Naoharu Shinozaki, Masao Taguchi, Akira Ogawa, Takuo Ito
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Patent number: 7317650Abstract: A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.Type: GrantFiled: March 9, 2007Date of Patent: January 8, 2008Assignee: Fujitsu LimitedInventors: Naoharu Shinozaki, Yasurou Matsuzaki
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Patent number: 7295483Abstract: A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.Type: GrantFiled: August 31, 2006Date of Patent: November 13, 2007Assignee: Fujitsu LimtedInventors: Naoharu Shinozaki, Yasurou Matsuzaki
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Publication number: 20070153613Abstract: A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.Type: ApplicationFiled: March 9, 2007Publication date: July 5, 2007Inventors: Naoharu Shinozaki, Yasurou Matsuzaki
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Patent number: 7209402Abstract: A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.Type: GrantFiled: October 20, 2004Date of Patent: April 24, 2007Assignee: Fujitsu LimitedInventors: Naoharu Shinozaki, Yasurou Matsuzaki
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Publication number: 20060291297Abstract: A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.Type: ApplicationFiled: August 31, 2006Publication date: December 28, 2006Inventors: Naoharu Shinozaki, Yasurou Matsuzaki
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Publication number: 20060285413Abstract: A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.Type: ApplicationFiled: August 24, 2006Publication date: December 21, 2006Inventors: Naoharu Shinozaki, Tatsuya Kanda, Takahiko Sato, Akihiro Funyu
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Patent number: 7113441Abstract: A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.Type: GrantFiled: February 15, 2005Date of Patent: September 26, 2006Assignee: Fujitsu LimitedInventors: Naoharu Shinozaki, Tatsuya Kanda, Takahiko Sato, Akihiro Funyu
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Publication number: 20060007770Abstract: A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.Type: ApplicationFiled: October 20, 2004Publication date: January 12, 2006Inventors: Naoharu Shinozaki, Yasurou Matsuzaki
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Patent number: 6963518Abstract: A pulse generator generates a plurality of column pulses in response to a read command. An address counter outputs addresses subsequent to an external address supplied in association with the read command in succession as internal addresses. A column decoder successively selects column selecting lines in synchronization with the column pulses. A plurality of bits of data read from memory cells in response to a single read command RD is successively transmitted to a common data bus line through column switches. This can reduce the number of data bus lines to a minimum, preventing an increase in chip size. Since a single data bus line can transmit a plurality of bits of data, it is possible to minimize the size of the memory region to be activated in response to a read command. This consequently allows a reduction in power consumption.Type: GrantFiled: March 14, 2003Date of Patent: November 8, 2005Assignee: Fujitsu LimitedInventors: Junichi Sasaki, Naoharu Shinozaki
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Publication number: 20050242864Abstract: Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock.Type: ApplicationFiled: February 11, 2005Publication date: November 3, 2005Inventors: Kenichi Kawasaki, Yasuharu Sato, Terumasa Kitahara, Masao Nakano, Masao Taguchi, Yoshihiro Takemae, Yasurou Matsuzaki, Koichi Nishimura, Yoshinori Okajima, Naoharu Shinozaki, Hiroko Douchi
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Publication number: 20050146968Abstract: A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.Type: ApplicationFiled: February 15, 2005Publication date: July 7, 2005Inventors: Naoharu Shinozaki, Tatsuya Kanda, Takahiko Sato, Akihiro Funyu
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Patent number: 6829192Abstract: A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.Type: GrantFiled: January 3, 2003Date of Patent: December 7, 2004Assignee: Fujitsu LimitedInventors: Naoharu Shinozaki, Yasurou Matsuzaki
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Patent number: 6707740Abstract: A plurality of sense amplifiers amplify parallel read data from memory cells, respectively. At least one of read amplifiers for amplifying the amplified read data respectively has a higher drivability than those of the rest of the read amplifiers. A connection switching circuit connects the sense amplifiers to a predetermined read amplifier according to an address. Switching the read data to one another before the amplification by the read amplifiers allows read data to be first outputted in burst read operation to be amplified by the read amplifier whose drivability is always high. In the burst read operation, a data output circuit first outputs read data corresponding to the read amplifier whose drivability is high. This enables reductions in read operation time and power consumption, even in a semiconductor memory in which the output orders of read data are changeable according to addresses or operation modes.Type: GrantFiled: March 25, 2002Date of Patent: March 16, 2004Assignee: Fujitsu LimitedInventor: Naoharu Shinozaki
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Publication number: 20040042334Abstract: A pulse generator generates a plurality of column pulses in response to a read command. An address counter outputs addresses subsequent to an external address supplied in association with the read command in succession as internal addresses. A column decoder successively selects column selecting lines in synchronization with the column pulses. A plurality of bits of data read from memory cells in response to a single read command RD is successively transmitted to a common data bus line through column switches. This can reduce the number of data bus lines to a minimum, preventing an increase in chip size. Since a single data bus line can transmit a plurality of bits of data, it is possible to minimize the size of the memory region to be activated in response to a read command. This consequently allows a reduction in power consumption.Type: ApplicationFiled: March 14, 2003Publication date: March 4, 2004Applicant: FUJITSU LIMITEDInventors: Junichi Sasaki, Naoharu Shinozaki
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Publication number: 20040008544Abstract: A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.Type: ApplicationFiled: January 3, 2003Publication date: January 15, 2004Applicant: FUJITSU LIMITEDInventors: Naoharu Shinozaki, Yasurou Matsuzaki