Abstract: An input conversion unit converts serial data supplied from the exterior into parallel data. Each of the converted parallel data is respectively written into a plurality of memory cell areas. An output conversion unit converts parallel data constructed by data read from each memory cell area into serial data. An operational unit is activated during a testing mode so as to logically operate on the parallel data read from each memory cell area. By writing predetermined data into each memory cell area in advance, it is confirmed by a logic operation that correct data is stored in each memory cell area. The data can be checked simultaneously for the plurality of memory cell areas so that the operation test in the memory cell areas can be carried out at high speed. Besides, serial data accepted, twice per cycle of a data strobe signal, is converted into parallel data. Each of the converted parallel data is respectively written into a first memory cell area and a second memory cell area.

Abstract: An address input circuit outputs an address signal from exterior as an internal address signal. A latching circuit accepts the internal address signal, and supplies the accepted signal to an internal circuit in conformity to the operating timing of the internal circuit. A redundancy judgement circuit judges whether or not the internal address signal yet to be accepted into the latching circuit is of a defect address, and outputs the judgement result as a redundancy judgement signal. A redundancy latching circuit accepts the redundancy judgement signal, and supplies the accepted signal to the internal circuit in conformity to the operating timing of the internal circuit. The use of the address signal before it is latched for redundancy judgement allows the redundancy judgement to be performed at earlier timing. Therefore, the amount of time needed for the read operation and write operation can be reduced.

Abstract: A command receiving circuit receives a command signal for determining a circuit operation, in synchronization with a clock signal and it outputs the received command signal as an internal command signal. An address switching circuit permits transmission of an address signal to an internal circuit upon receiving the command signal. The internal circuit receives the address signal before the reception of the command signal, thereby to start its operation. As a result, the internal circuit can be operated at high speed. Besides, the address switching circuit inhibits the transmission of the address signal to the internal circuit upon receiving the internal command signal or the clock signal. Therefore, even when the level of the address signal has changed after the reception of the command signal, the change does not lead to operating the internal circuit. Accordingly, the power consumption of the semiconductor integrated circuit is reduced.

Abstract: Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock.

Abstract: A semiconductor integrated circuit comprising a memory cell, a column switch for transmitting data to a bit line, a sense amplifier for amplifying data, a precharging circuit for charging the bit line, and a control unit. The control unit controls the transfer switch in the memory cell, the column switch, the sense amplifier, and the precharging circuit so as to differentiate the control timings of these circuits between a write operation and a read operation. For example, the column switch is turned on after the transfer switch is turned on and before the amplification of the sense amplifier is started in a write operation. Here, the data retained in the memory cell are rewritten into write data before amplified by the sense amplifier. This minimizes the data inversion time and heightens the speed of write operations. The power consumption can be reduced since the circuits optimally operate in accordance with the operating modes.

Abstract: A semiconductor device receiving a stable external power voltage includes a reduced-voltage-generation circuit which generates an internally reduced power voltage, an input circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, a clock-control circuit which generates an internal clock signal, an output circuit which outputs a data signal to an exterior of the device at output timings responsive to the internal clock signal, a clock-delivery circuit which conveys the internal clock signal from the clock-control circuit to the output circuit, and operates based on the external power voltage such as to make the output timings substantially unaffected by fluctuation of the internally reduced power voltage.

Abstract: The semiconductor integrated circuit comprises a memory cell, a sense amplifier, input/output controlling circuit, a switch circuit which connects the sense amplifier and the input/output circuit, a reference timing signal generator, a timing controlling circuit having a delay element, and a switch controlling circuit which controls the switch circuit. The reference timing signal generator generates a reference timing signal necessary for read/write operations. The timing controlling circuit receives the reference timing signal and generates, by using the delay element thereof, at least one of either a read controlling signal or a write controlling signal whose timing shifts from the timing of the switch controlling signal by a predetermined amount of time. Therefore, the deviation between the timings of the switch controlling signal and the read controlling signal or the write controlling signal can easily be set to a predetermined value.

Abstract: A semiconductor memory circuit includes a circuit which generates a test mode entry signal which enables a test mode directed to evaluating the semiconductor memory circuit. The circuit generates the test mode entry signal on the basis of a plurality of combinations of a predetermined command signal sequentially applied from an outside of the semiconductor memory circuit.

Abstract: The semiconductor integrated circuit comprises a memory cell, a sense amplifier, input/output controlling circuit, a switch circuit which connects the sense amplifier and the input/output circuit, a reference timing signal generator, a timing controlling circuit having a delay element, and a switch controlling circuit which controls the switch circuit. The reference timing signal generator generates a reference timing signal necessary for read/write operations. The timing controlling circuit receives the reference timing signal and generates, by using the delay element thereof, at least one of either a read controlling signal or a write controlling signal whose timing shifts from the timing of the switch controlling signal by a predetermined amount of time. Therefore, the deviation between the timings of the switch controlling signal and the read controlling signal or the write controlling signal can easily be set to a predetermined value.

Abstract: The present invention is a memory device having a multiple-bit data pre-fetch function wherein the operation of a redundancy checking circuit for comparing addresses and redundant addresses and checking the coincidence or non-coincidence thereof is started with timing prior to performing the last data fetches. The address signals are supplied with the same timing as the supply of the write commands, wherefore it is not always necessary for the operation of comparing the address signals against the redundant addresses of the memory cells, where the switch to the redundant cell array was performed, to have to wait until all of the multiple-bit data to be fetched. Accordingly, with the present invention, the redundancy checking operation is started before all of the data are fetched. In the case of a 2-bit data pre-fetch, the redundancy checking operation is started after the first datum has been fetched, and before the second bit of data is fetched.

Abstract: A pipe-line control of internal circuits is performed by an internal clock whose timing does not depend on a predetermined phase difference to the phase of an external clock. To control the timing of the output signal from an output circuit to the predetermined phase difference with respect to the phase of the external clock, a delay circuit is inserted at the subsequent stage of the last stage of pipe-line gate. The delay time of this delay circuit is so controlled as to set the timing of the output signal to have the predetermined phase difference to the phase of the external clock.

Abstract: A load adjusting circuit 36 adjusts the load value L=L2 of a dummy load circuit 31x corresponding to the outputs of a frequency determining circuit 37 and an interface determining circuit 35 as L2=L1-.DELTA.L holding, where L=L1 is a proper value in the case that the access time does not depend on the frequency of the data DQ and .DELTA.L corresponds to a half of the maximum value tlc of the deviation of the access time that varies corresponding to the frequency of the data DQ. A DLL circuit 40 delays a internal clock iCLK by a time .delta.tx so that a difference between phases of the clock iCLK and a dummy internal clock d.sub.-- iCLK becomes a predetermined value. The delay time .delta.tx is equal to a value determined in such a way that .delta.tx=67 tx0 is determined with activating the DLL circuit 40, tlc is determined and .delta.tx is finally determined as .delta.tx=.delta.tx0+ tlc/2 or .delta.tx=.delta.tx0-tlc/2 due to the condition of data frequency at determining .delta.tx0.

Abstract: An internal step-down power supply circuit for lowering an external power supply voltage supplied from outside to an internal power supply voltage in a semiconductor device includes a circuit for generating the internal power supply voltage in response to a control voltage, potential regulation circuits for a normal operation and for a test operation, respectively, having fuse elements for making it possible to regulate the potential of the control circuit, and potential control circuits disposed for the normal operation and for the test operation, respectively, for controlling the potential of the control voltage on the basis of the output of the corresponding potential regulation circuit. The external power supply voltage is used as a power supply of the potential regulation circuit for the normal operation and the internal power supply voltage is used as a power supply of the potential regulation circuit for the test operation.

Abstract: A semiconductor device which performs a predetermined operation includes a timing-stabilization circuit which performs a timing adjustment with respect to an internal clock signal, and a current-consumption circuit which consumes a predetermined amount of a current so as to emulate conditions of such current consumption as would be observed during the predetermined operation of the semiconductor device. The semiconductor device further includes a start-up-period control circuit which makes the timing-stabilization circuit and the current-consumption circuit operate at a beginning of power supply so as to perform the timing adjustment under the conditions, and stops operations of the timing-stabilization circuit and the current-consumption circuit after completion of the timing adjustment.

Abstract: A semiconductor device, equipped with a circuit for regulating an internal power source by using a plurality of fuses, includes a fuse group for trimming a power source, having a plurality of fuses capable of being cut off so as to regulate a voltage level of an internal power source; a decoding unit for fuse information of the internal power source, for decoding fuse information in response to a cut-off state of each of these fuses and outputting bit information corresponding to the thus regulated voltage level of the internal power source; and a voltage level regulating unit for a spare fuse pattern, for generating at least one spare pattern other than patters of the bit information used at present and for regulating the voltage level of the internal power source. The voltage level of the internal power source is regulated so that the spare pattern corresponds to any one of the patterns of the bit information used at present.

Abstract: A booster circuit is used to boost a first voltage using a capacitor unit so as to generate a second voltage. The capacitor unit has at least one MOS capacitor each formed by a MOS transistor, and at least one conductive electrode capacitor, each connected in parallel with corresponding MOS capacitor. Each conductive electrode capacitor includes a first conductive electrode and a second conductive electrode which are mutually opposed, and a dielectric layer interposed between the first and second conductive electrodes. Therefore, the low-voltage operating point margin of the booster circuit can be expanded while an increase in the area occupied by the booster circuit is suppressed.

Abstract: A semiconductor memory device includes a memory cell portion and at least one output part being provided with a plurality of read data which are read from the memory cell portion and a mode selection signal. The output part has a logic decision circuit for producing a control signal indicating whether logic levels of the plurality of read data are all the same, and an output circuit controlling to operate in at least one of two states, a first state being to transmit first read data of the plurality of read data to an output port of the output circuit and a second state being to set the output port to be at a high-impedance state depending on the control signal and the mode selection signal. In the output part, when the mode selection signal indicates a normal mode, the output circuit operates in said first state, and when the mode selection signal indicates a test mode, the output circuit operates in one of said first state and said second state depending on the control signal.

Abstract: A semiconductor device which allows an input signal thereto to select one of N operation modes, and operates in the one of N operation modes includes a selection circuit for selecting an operation mode from the N operation modes when the input signal indicates the operation mode, and for selecting a predetermined operation mode from the N operation modes when the input signal is an undefined signal indicating none of the N operation modes. The semiconductor device further includes an internal circuit operating in an operation mode selected by the selection circuit.

Abstract: A synchronous semiconductor device operates in synchronism with clock signal supplied from an external unit. The synchronous semiconductor device can be set in a first mode (a CSUS mode) and a power down mode (a PD mode) as an operation mode when a predetermined external signal (a CKE signal) is in a predetermined state.

Abstract: There is provided a method of controlling data transmission lines of a semiconductor memory device which has a first pair of data transmission lines to which a sense amplifier and memory cells are connected, and a second pair of data transmission lines to which a read circuit and a write circuit are connected at an end of the second pair of the data transmission lines, which is connected to the first pair of data transmission lines via a column gate. The method includes a) shortcircuiting the second pair of data transmission lines for a first period when a read operation is carried out, and b) shortcircuiting the second pair of data transmission lines for a second period when a write operation is carried out, the second period being shorter than the first period.