Abstract: A mode register control circuit for a semiconductor device includes a first control unit for preventing the content of a mode register from being read, using an initializing signal for instructing latching circuits to be initialized, the initialization being done in a transient occurring after the semiconductor device is turned on; a second control unit for instructing the mode register to execute a mode register read command even if a mode register set command has not been executed, on the condition that an external command other than the mode register read command is detected when the semiconductor device is turned on; or a third control unit for instructing the mode register to execute the mode register read command on the condition that the mode register set command is executed after the semiconductor device is turned on.

Abstract: An SDRAM offering an increased operating speed and needing a limited area for layout is provided. In the synchronous DRAM, at least part of the signal processing to be executed continually is divided into a plurality of steps, the plurality of steps are executed concurrently in synchronization with an external clock applied externally, and thus the operating speed is increased. The synchronous DRAM comprises a plurality of pipes (i.e.

Abstract: A DRAM to which a setting can be made to determine an internal operation frequency thereof includes a memory cell array, sense amplifiers writing data to and reading data from the memory cell array, a pair of data-bus lines, and gates connecting between the pair of data-bus lines and the sense amplifiers, the gates providing the pair of data-bus lines with access to the sense amplifiers when the gates are open. The DRAM further includes a control circuit controlling a period of the access to be a different period for a different setting of the internal operation frequency.

Abstract: A mode register control, circuit for a semiconductor device includes a first control unit for preventing the content of a mode register from being read, using an initializing signal for instructing latching circuits to be initialized, the initialization being done in a transient occurring after the semiconductor device is turned on; a second control unit for instructing the mode register to execute a mode register read command even if a mode register set command has not been executed, on the condition that an external command other than the mode register read command is detected when the semiconductor device is turned on; or a third control unit for instructing the mode register to execute the mode register read command on the condition that the mode register set command is executed after the semiconductor device is turned on.

Abstract: There is provided a method of controlling data transmission lines of a semiconductor memory device which has a first pair of data transmission lines to which a sense amplifier and memory cells are connected, and a second pair of data transmission lines to which a read circuit and a write circuit are connected at an end of the second pair of the data transmission lines, which is connected to the first pair of data transmission lines via a column gate. The method includes a) shortcircuiting the second pair of data transmission lines for a first period when a read operation is carried out, and b) shortcircuiting the second pair of data transmission lines for a second period when a write operation is carried out, the second period being shorter than the first period.

Abstract: A synchronous semiconductor device operates in synchronism with clock signal supplied from an external unit. The synchronous semiconductor device can be set in a first mode (a CSUS mode) and a power down mode (a PD mode) as an operation mode when a predetermined external signal (a CKE signal) is in a predetermined state.