Abstract: A solid object detection device includes an overhead view transformation processing unit transforming first and second photographed images photographed by a camera at different timings in travel of a vehicle into first and second overhead view images, respectively, a subtracted image generation unit generating a subtracted image between the first and second overhead view images whose photographing positions are aligned with each other, a solid object position specification unit specifying a position of a solid object present around the vehicle based on the subtracted image, and a masked subtracted image generation unit generating a masked subtracted image in which a region other than a solid object candidate region as a candidate where the solid object appears in the subtracted image is masked and the solid object position specification unit specifies a position of the solid object in the subtracted image based on the masked subtracted image.

Abstract: The present invention addresses the problem of enabling an accurate determination of line type using a plurality of cameras.

Abstract: A section line recognition device is realized which can determine a line type of a section line in a road surface with high accuracy. In step 301, a feature amount is extracted from an image captured by each camera. This step corresponds to a process of a feature point extraction unit. In the next step 302, the extracted feature amount is transformed into bird's-eye view coordinates which is common coordinates. This step corresponds to a process of a coordinates transformation unit. Next, in step 303, a camera to be selected is determined. This step is a process of a camera determination unit. Next, in step 304, the state transition at the appearance position of the feature point on the bird's-eye view coordinates is determined using feature point coordinates of the camera selected in step 303. This step is a process of a state transition determination unit. Finally, in step 305, the line type is determined. This step is a process of a line type determination unit.

Abstract: A system and a method which allow an easy shipment and receipt of construction materials and an easy retrieval of the same, as well as an easy acquisition of position information of construction materials. The system includes: an identification information holding medium which holds identification information of the construction material; a moving body that acquires first position information which is position information of the moving body and also acquires identification information; material data storage unit for storing the first position information in association with the identification information; and retrieval unit for retrieving the identification information in the material data storage unit. The display unit displays the first position information associated with the identification information retrieved by the retrieval unit.

Abstract: A tactile presentation device includes: a substrate including a vibration plate and a terminal plate which are integrally formed; an actuator that is provided on the vibration plate, and generates a standing wave of ultrasonic vibration; a terminal that is provided on an end of the terminal plate, and electrically connects the actuator to an external; a fixing member that fixes the vibration plate to a support; and a vibration suppressor that is provided between the terminal and the fixing member, and suppresses the ultrasonic vibration transmitted from the vibration plate to the support.

Abstract: A semiconductor memory device includes nonvolatile memory cells. A first circuit is configured to receive data to be written to the plurality of memory cells, read data from the plurality of memory cells, compare the data to be written to the data that was read, identify each memory cell presently storing a data value that differs from a data value to be written, and identify weak bit data in the existing data. A second circuit is configured to simultaneously program the weak bits and memory cells identified as presently storing the data value that differs from the data value to be written to the memory cell.

Abstract: According to one embodiment, a memory device includes one or more semiconductor devices connected in common to a bus. Each of the one or more semiconductor devices includes a memory unit to store data, and an input/output control unit. The input/output control unit is configured to acquire address information from a data processing device via the bus and access the memory unit according to the acquired address information. The data processing device is configured to divide the address information into a plurality of cycles to transmit to the bus. The input/output control unit is configured to switch a number of cycles in which the address information is to be acquired, according to setting information acquired from the data processing device.

Abstract: A piezoelectric member including metal electrodes with improved adhesiveness to piezoelectric elements is to be provided. A piezoelectric member 102 includes a piezoelectric element 21, and a pair of electrodes 41, 42 respectively formed on a pair of opposing surfaces 21b, 21c of the piezoelectric element 21. The electrodes 41, 42 includes: a base film 41a that is formed on the opposing surfaces 21b, 21c of the piezoelectric element 21 and contains a thiol group; a metal adhesive film 41b formed on the base film 41a; and an electrode film 41c that is formed on the metal adhesive film 41b and is for applying voltage to the piezoelectric element 21. The metal adhesive film 41b is formed with a different material from the electrode film 41c, and has a thickness of 1 to 10 nm.

Abstract: Power cycle life of an intelligent power module that includes an IGBT is estimated by an abnormality detection circuit(s) while a chip temperature detection circuit or a case temperature detection circuit is outputting a chip overheating warning signal or a case overheating warning signal. Once the estimated power cycle life has reached a prescribed value, the abnormality detection circuit outputs an abnormality detection signal to forcedly and permanently stop operation of a driver circuit that drives an IGBT. The abnormality detection circuit may include a prescribed period calculation circuit that calculates the duration of the warning signal, a prescribed count calculation circuit that calculates the number of times the warning signal has been generated, and/or a cumulative time calculation circuit that calculates that the cumulative duration of periods in which the warning signal has been generated so as to estimate the power cycle life of the intelligent power module.

Abstract: According to one embodiment, a memory system includes a resistance change type memory including a memory cell configured to hold first data and an ECC circuit configured to detect and to correct an error in the first data; and a controller configured to control an operation of the resistance change type memory. In a read operation for the memory, when the first data from the memory cell includes an error, the memory transmits second data in which the error is corrected and a first signal to the controller. The controller transmits a control signal and a write command to the memory based on the first signal. The memory writes the second data to the memory cell based on the control signal and the write command.

Abstract: The present invention provides a piezoelectric element manufacturing method. The manufacturing method is a method of manufacturing a piezoelectric element comprising a piezoelectric body composite in which a piezoelectric body configured from a Pb-based piezoelectric material and a resin are alternately arranged, and comprises a step of etching, using an etching liquid, a plurality of parallel piezoelectric body segments formed by dicing. The etching liquid comprises a liquid which contains 0.1 to 20 mass % of hexafluorosilicic acid.

Abstract: A tactile presentation device includes: a substrate that has a lower surface on which a vibration generation element is mounted, and an upper surface opposite to the lower surface; a first adhesive layer that is disposed on the upper surface of the substrate; a first elastic layer that is disposed on the first adhesive layer, and has a lower elastic modulus than an elastic modulus of the substrate; wherein the elastic modulus of the first elastic layer corresponding to a frequency of an ultrasonic band of the vibration generation element is equal to or more than 1 GPa.

Abstract: A semiconductor memory device includes nonvolatile memory cells. A first circuit is configured to receive data to be written to the plurality of memory cells, read data from the plurality of memory cells, compare the data to be written to the data that was read, identify each memory cell presently storing a data value that differs from a data value to be written, and identify weak bit data in the existing data. A second circuit is configured to simultaneously program the weak bits and memory cells identified as presently storing the data value that differs from the data value to be written to the memory cell.

Abstract: According to one embodiment, a semiconductor memory device includes a nonvolatile memory comprising a plurality of memory cells, and a controller configured to perform, a preliminary write process of writing reverse data into a first memory cell, and a main write process of writing correct data in the first memory cell, when the first memory cell is in a weak bit state, wherein a condition of the preliminary write process is different from a condition of the main write process.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell having a first variable resistance element, a second memory cell having a second variable resistance element, and a first circuit which controls writing to the first memory cell and the second memory cell. The first circuit receives a first command instructing writing to the first memory cell, after receiving the first command, receives a second command instructing writing to the second memory cell, and after receiving the second command, performs writing to the second memory cell when performing writing to the first memory cell.

Abstract: According to one embodiment, a memory device includes a memory area; and a control circuit, in response to a first command, configured to read out data from the memory area without outputting the data to a data line, subsequently, in response to a second command, configured to output the data to the data line, if the first command is not received after receiving an active command, in response to the second command, configured to output the data read out from the memory area to the data line.

Abstract: To provide a driving device for semiconductor elements that is capable of suppressing variation in switching time caused by driving capability and temperature. A driving device for semiconductor elements includes: a semiconductor chip in which a voltage control type semiconductor element is formed; a temperature detecting unit configured to detect temperature of the semiconductor chip; a driving-capability adjusting unit configured to adjust driving capability of the voltage control type semiconductor element according to temperature detection values detected by the temperature detecting unit; and a timing adjusting unit configured to adjust switching time of the voltage control type semiconductor element according to the temperature detection values detected by the temperature detecting unit.

Abstract: According to one embodiment, a semiconductor memory device comprises a memory cell including a variable resistance element; and a first circuit configured to control writing to the memory cell. The first circuit is configured to generate a first pulse of a second signal based on a first signal from outside, generate a second pulse of a third signal obtained by delaying the first pulse, and generate a third pulse of a fourth signal obtained by delaying the second pulse. A falling edge of the first pulse is based on a rising edge of the second pulse. A write pulse is output based on the fourth signal.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array with a plurality of memory cells, an ECC circuit with an encoder for generating error correcting codes and a decoder for performing correcting processing, a page buffer capable of storing the write data, corrected data, and the error correcting codes, and a multiplexer having a first input terminal coupled to the encoder, a second input terminal coupled to the page buffer, and an output terminal coupled to the memory cell array, in which the first input terminal is selected when writing the write data in the plurality of memory cells and the second input terminal is selected when writing the corrected data in the plurality of memory cells.

Abstract: According to one embodiment, a semiconductor memory device includes a nonvolatile memory comprising a plurality of memory cells, and a controller configured to perform, a preliminary write process of writing reverse data into a first memory cell, and a main write process of writing correct data in the first memory cell, when the first memory cell is in a weak bit state, wherein a condition of the preliminary write process is different from a condition of the main write process.