Abstract: According to one embodiment, a memory device includes one or more semiconductor devices connected in common to a bus. Each of the one or more semiconductor devices includes a memory unit to store data, and an input/output control unit. The input/output control unit is configured to acquire address information from a data processing device via the bus and access the memory unit according to the acquired address information. The data processing device is configured to divide the address information into a plurality of cycles to transmit to the bus. The input/output control unit is configured to switch a number of cycles in which the address information is to be acquired, according to setting information acquired from the data processing device.

Abstract: According to one embodiment, a semiconductor memory device that is not equipped with an operating state notification terminal for providing notification of the operating state of the memory device includes a data bus comprising a plurality of signal lines and a controller configured to adjust an impedance of a signal line when the memory device is in a busy state and cannot receive signals transmitted thereto so as to provide notification of the operating state of the memory device during ZQ calibration.

Abstract: An information processing apparatus is connected to a plurality of online storages through a network. The apparatus includes a circuitry to divide a file into a plurality of pieces of segment data, encrypt each of the plurality of segment data with an encryption key, and generate a plurality of final generated files, each including the encryption key and at least one piece of the plurality of segment data encrypted with the encryption key, and a transmitter to transmit each one of the plurality of final generated files to a corresponding one of the plurality of online storages. The circuitry manages folder and file management information that associates a folder path of each of the folders stored in the online storages with a virtual folder path, and associates a file path of each of the final generated files stored in the online storages with a virtual file path.

Abstract: A position of a moving object is reliably detected with high accuracy using only an image around a vehicle. A rear camera mounted on a vehicle obtains an original image around the vehicle, a movement region detector detects a moving object from the original image, and a difference calculator detects the moving object from a bird's-eye view image of the vehicle generated by a bird's-eye view image processor. A moving object position identifying part identifies a position of the moving object based on a distance from the vehicle to the moving object detected by the movement region detector or the difference calculator, a lateral direction position of the moving object, and an actual width of the moving object detected by the movement region detector when a detected object determination part determines that the moving objects detected by the movement region detector and the difference calculator are the same moving object.

Abstract: To provide a transfer apparatus correcting a curl of a card efficiently while preventing the card from deteriorating, a printing apparatus includes a transfer section transferring a transfer surface of a transfer film to the card, a rotating unit reversing the front side and back side of the card in two-sided transfer, a decurl mechanism correcting a curl of the card with the transfer surface transferred in the transfer section, and a control section controlling the decurl mechanism. The control section controls the decurl mechanism such that a correction amount for the card with the transfer surface transferred to one surface in two-sided transfer is smaller than a correction amount for the card in one-sided transfer, and that the total sum of correction amounts for respective surfaces of the card in two-sided transfer is smaller than the correction amount for the card in one-sided transfer.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell having a first variable resistance element, a second memory cell having a second variable resistance element, and a first circuit which controls writing to the first memory cell and the second memory cell. The first circuit receives a fir command instructing writing to the first memory cell, after receiving the first command, receives a second command instructing writing to the second memory cell, and after receiving the second command, performs writing to the second memory cell when performing writing to the first memory cell.

Abstract: According to one embodiment, a memory system includes a resistance change type memory including a memory cell configured to hold first data and an ECC circuit configured to detect and to correct an error in the first data; and a controller configured to control an operation of the resistance change type memory. In a read operation for the memory, when the first data from the memory cell includes an error, the memory transmits second data in which the error is corrected and a first signal to the controller. The controller transmits a control signal and a write command to the memory based on the first signal. The memory writes the second data to the memory cell based on the control signal and the write command.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array with a plurality of memory cells, an ECC circuit with an encoder for generating error correcting codes and a decoder for performing correcting processing, a page buffer capable of storing the write data, corrected data, and the error correcting codes, and a multiplexer having a first input terminal coupled to the encoder, a second input terminal coupled to the page buffer, and an output terminal coupled to the memory cell array, in which the first input terminal is selected when writing the write data in the plurality of memory cells and the second input terminal is selected when writing the corrected data in the plurality of memory cells.

Abstract: According to one embodiment, a semiconductor memory device comprises a memory cell and a first circuit. The first circuit is configured to generate a write pulse based on a write command and supply a write current to the memory cell in accordance with the write pulse. The first circuit generates a first write pulse when the first circuit receives a first write command. The first circuit extends the first write pulse when the first circuit receives a second write command within a first time after reception of the first write command.

Abstract: A system and a method which allow an easy shipment and receipt of construction materials and an easy retrieval of the same, as well as an easy acquisition of position information of construction materials. The system includes: an identification information holding medium which holds identification information of the construction material; a moving body that acquires first position information which is position information of the moving body and also acquires identification information; material data storage unit for storing the first position information in association with the identification information; and retrieval unit for retrieving the identification information in the material data storage unit. The display unit displays the first position information associated with the identification information retrieved by the retrieval unit.

Abstract: To provide a driving device for semiconductor elements that is capable of suppressing variation in switching time caused by driving capability and temperature. A driving device for semiconductor elements includes: a semiconductor chip in which a voltage control type semiconductor element is formed; a temperature detecting unit configured to detect temperature of the semiconductor chip; a driving-capability adjusting unit configured to adjust driving capability of the voltage control type semiconductor element according to temperature detection values detected by the temperature detecting unit; and a timing adjusting unit configured to adjust switching time of the voltage control type semiconductor element according to the temperature detection values detected by the temperature detecting unit.

Abstract: A nonvolatile random access memory including a memory cell array including banks, each bank including rows; an address latch circuit; and a control circuit receiving a first set of signals including a precharge command and a first row address, and a second set of signals including an active command and a second row address. The control circuit executes a first operation in which one of the banks is deactivated when the first set of signals is loaded, executes a second operation in which the first row address is loaded when the first set of signals is loaded, and executes a third operation in which at least one of the rows in the bank is selected and activated based on the second row address when the second set of signals is loaded after the first set of signals.

Abstract: A memory device includes: a memory cell; a data buffer which receives write data; a first latch circuit which latches data stored in the memory cell; a second latch circuit which latches data transferred from the data buffer; a controller which performs a first transfer operation to transfer data from the data buffer to the second latch circuit after a write command is received and then a first period elapses; and a write circuit which performs a write operation to write data of the second latch circuit to the memory cell after the first transfer operation, when data of the first latch circuit is different from the data of the second latch circuit. The controller performs a second transfer operation to transfer data from the second latch circuit to the first latch circuit after the write operation.

Abstract: A memory device includes: a memory cell array including memory cells; a correction circuit which encodes write data and generates an error correction signal, in a first period; a write circuit which writes the write data to a memory cell in a second period following the first period; a first circuit which receives a first signal generated based on a write command, generates a first clock signal having a first cycle from the first signal, and sets the first period with the first clock signal; and a second circuit which receives the first clock signal, generates a second clock signal having a second cycle from the first clock signal, and sets the second period with the second clock signal.

Abstract: A memory device includes: a memory cell array including memory cells; a correction circuit which encodes write data and generates an error correction signal, in a first period; a write circuit which writes the write data to a memory cell in a second period following the first period; a first circuit which receives a first signal generated based on a write command, generates a first clock signal having a first cycle from the first signal, and sets the first period with the first clock signal; and a second circuit which receives the first clock signal, generates a second clock signal having a second cycle from the first clock signal, and sets the second period with the second clock signal.

Abstract: According to one embodiment, a semiconductor memory device comprises a memory cell including a variable resistance element; and a first circuit configured to control writing to the memory cell. The first circuit is configured to generate a first pulse of a second signal based on a first signal from outside, generate a second pulse of a third signal obtained by delaying the first pulse, and generate a third pulse of a fourth signal obtained by delaying the second pulse. A falling edge of the first pulse is based on a rising edge of the second pulse. A write pulse is output based on the fourth signal.

Abstract: A memory device includes: a memory cell; a data buffer which receives write data; a first latch circuit which latches data stored in the memory cell; a second latch circuit which latches data transferred from the data buffer; a controller which performs a first transfer operation to transfer data from the data buffer to the second latch circuit after a write command is received and then a first period elapses; and a write circuit which performs a write operation to write data of the second latch circuit to the memory cell after the first transfer operation, when data of the first latch circuit is different from the data of the second latch circuit. The controller performs a second transfer operation to transfer data from the second latch circuit to the first latch circuit after the write operation.

Abstract: The battery pack includes a battery cell for supplying electric power to an external device connected thereto, a temperature sensor for sensing a temperature of a place on which the temperature sensor is arranged, a switch member for making and breaking an electric path between the external device and the battery cell; and a controller configured to control the switch member to turn on and off according to the temperature sensed by the temperature sense. The temperature sensor is arranged on a position between the battery cell and the switch member so as to be affected by the temperatures of both of the battery cell and the switch member.

Abstract: A method of controlling a magnetoresistive random access memory includes receiving first signals associated with an active state through command/address pins; then receiving second signals associated with column and row addresses for a read operation, through the command/address pins, and in response reading data from a memory cell according to the row address; receiving third signals associated with column and row addresses for a write operation through the command/address pins, while reading the data; outputting the read data to data input/output pins, according to the column address for the read operation, after a lapse of a read latency; inputting data through the data input/output pins, in response to the third signals, according to the column address for the write operation, after a lapse of a write latency; and writing the data inputted from the data input/output pins to a memory cell according to the row address for the write operation.

Abstract: Disclosed is technology for providing guidance in a manner that facilitates travel along a guidance route when there is a road which has a carpool lane. A navigation device (100) is provided with: a current-location calculation means for calculating the current location of a moving body; a recommended route search means for searching for a recommended route to a destination; a guidance-point setting means for setting a guidance point in the recommended route; and a guidance information notification means for notifying predetermined guidance information when a moving body reaches a set guidance point. When predetermined conditions are fulfilled, the guidance-point setting means sets in a road which has a carpool lane a guidance point for notifying information for guidance from said road to a branch road, before the guidance point that would be set in a road that does not have a carpool lane.