Abstract: A vehicle suspension structure includes a suspension arm and a ball joint. The suspension arm is connected between a suspension member and a vehicle-widthwise outer side end connected to a vehicle wheel. The ball joint connects the suspension arm and the vehicle wheel. When the vehicle receives an impact in the longitudinal direction, a socket of the ball joint pivots relative to a ball as the suspension arm deforms, and a flange portion on an open side of the socket interferes with a stud shaft of the ball joint. The interference causes the flange portion to deform and the ball to come out of the socket to undo the link with the vehicle wheel by the ball joint. Upon becoming unlinked, the vehicle wheel moves toward the vehicle-widthwise outer side and interference with the rear vehicle body is suppressed to limit deformation of the vehicle body.

Abstract: A ceramic body is prepared that includes an inner electrode disposed inside the ceramic body and in which an end portion of the inner electrode is led to a surface of the ceramic body. An electrode layer is formed on the surface of the ceramic body so as to cover the end portion of the inner electrode, the electrode layer containing a resin, a first metal filler that contains a first metal component, and a second metal filler that contains a second metal component having a higher melting point than the first metal component. A heating step of heating the electrode layer is performed to form an electrode including a metal layer that is located on the surface of the ceramic body and that contains the first and second metal components and a metal contained in the inner electrode.

Abstract: A semiconductor memory device contains a first memory cell including a first variable resistive element, and a first circuit for controlling a write performed for the first memory cell. The first circuit performs a first write for writing first data in the first memory cell in a first time, determines whether the first write fails or not, and performs a second write for writing the first data in the first memory cell in a second time longer than the first time, if the first write fails.

Abstract: According to one embodiment, a semiconductor memory device comprises a memory cell and a first circuit. The first circuit is configured to generate a write pulse based on a write command and supply a write current to the memory cell in accordance with the write pulse. The first circuit generates a first write pulse when the first circuit receives a first write command. The first circuit extends the first write pulse when the first circuit receives a second write command within a first time after reception of the first write command.

Abstract: A semiconductor memory device contains a first memory cell including a first variable resistive element, and a first circuit for controlling a write performed for the first memory cell. The first circuit performs a first write for writing first data in the first memory cell in a first time, determines whether the first write fails or not, and performs a second write for writing the first data in the first memory cell in a second time longer than the first time, if the first write fails.

Abstract: A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows in each of the banks; and an address latch circuit configured to latch a full address specifying one of the word lines, the full address including a first address and a second address. The address latch circuit receives a first command and a second command to latch the first address and the second address in accordance with the first command and the second command, respectively. Paths for the first address and the second address are configured to be separate from each other.

Abstract: A memory device according to one embodiment includes a memory cell which transitions to a first state or a second state by a first current through the memory cell; and a first circuit configured to stop supplying the first current when a first number of cycles of a clock signal lapses from reception of write data.

Abstract: A nonvolatile random access memory including a memory cell array including banks, each bank including rows; an address latch circuit; and a control circuit receiving a first set of signals including a precharge command and a first row address, and a second set of signals including an active command and a second row address. The control circuit executes a first operation in which one of the banks is deactivated when the first set of signals is loaded, executes a second operation in which the first row address is loaded when the first set of signals is loaded, and executes a third operation in which at least one of the rows in the bank is selected and activated based on the second row address when the second set of signals is loaded after the first set of signals.

Abstract: An information processing apparatus includes an acceptance unit that accepts a configuration of a cooperative operation to be performed by multiple apparatuses cooperating with each other, an execution order determination unit that determines an executing order of processes included in the cooperative operation, an apparatus determination unit that identifies, for each of the processes included in the cooperative operation, an apparatus that performs the process, and a controller that instructs the identified apparatus to execute the processes included in the cooperative operation in the determined executing order.

Abstract: A position of a moving object is reliably detected with high accuracy using only an image around a vehicle. A rear camera mounted on a vehicle obtains an original image around the vehicle, a movement region detector detects a moving object from the original image, and a difference calculator detects the moving object from a bird's-eye view image of the vehicle generated by a bird's-eye view image processor. A moving object position identifying part identifies a position of the moving object based on a distance from the vehicle to the moving object detected by the movement region detector or the difference calculator, a lateral direction position of the moving object, and an actual width of the moving object detected by the movement region detector when a detected object determination part determines that the moving objects detected by the movement region detector and the difference calculator are the same moving object.

Abstract: A substrate with a built-in capacitor includes an insulating base material layer, a build-up layer formed on the insulating base material layer and including a conductor layer and an insulating layer, and a multilayer ceramic capacitor positioned in an opening of the base material layer and including internal electrodes, ceramic dielectric layers and a pair of external electrodes. The ceramic capacitor has a cuboid shape having long sides and short sides, the pair of external electrodes is formed on opposing long-side sides such that the external electrodes are separated by a distance in range of 30 ?m to 200 ?m and that each external electrode includes a conductive paste layer connected to a respective group of the internal electrodes and a copper plated layer covering the conductive paste layer, and the conductive paste layer includes Ni paste or Cu paste including glass component in range of 5% to 40%.

Abstract: An information processing apparatus is connected to a plurality of online storages through a network. The apparatus includes a circuitry to divide a file into a plurality of pieces of segment data, encrypt each of the plurality of segment data with an encryption key, and generate a plurality of final generated files, each including the encryption key and at least one piece of the plurality of segment data encrypted with the encryption key, and a transmitter to transmit each one of the plurality of final generated files to a corresponding one of the plurality of online storages. The circuitry manages folder and file management information that associates a folder path of each of the folders stored in the online storages with a virtual folder path, and associates a file path of each of the final generated files stored in the online storages with a virtual file path.

Abstract: According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.

Abstract: A method of controlling a magnetoresistive random access memory includes receiving first signals associated with an active state through command/address pins; then receiving second signals associated with column and row addresses for a read operation, through the command/address pins, and in response reading data from a memory cell according to the row address; receiving third signals associated with column and row addresses for a write operation through the command/address pins, while reading the data; outputting the read data to data input/output pins, according to the column address for the read operation, after a lapse of a read latency; inputting data through the data input/output pins, in response to the third signals, according to the column address for the write operation, after a lapse of a write latency; and writing the data inputted from the data input/output pins to a memory cell according to the row address for the write operation.

Abstract: A memory device according to one embodiment includes a memory cell which transitions to a first state or a second state by a first current through the memory cell; and a first circuit configured to stop supplying the first current when a first number of cycles of a clock signal lapses from reception of write data.

Abstract: A vehicle suspension structure includes a suspension arm and a ball joint. The suspension arm is connected between a suspension member and a vehicle-widthwise outer side end connected to a vehicle wheel. The ball joint connects the suspension arm and the vehicle wheel. When the vehicle receives an impact in the longitudinal direction, a socket of the ball joint pivots relative to a ball as the suspension arm deforms, and a flange portion on an open side of the socket interferes with a stud shaft of the ball joint. The interference causes the flange portion to deform and the ball to come out of the socket to undo the link with the vehicle wheel by the ball joint. Upon becoming unlinked, the vehicle wheel moves toward the vehicle-widthwise outer side and interference with the rear vehicle body is suppressed to limit deformation of the vehicle body.

Abstract: A ceramic electronic component includes a ceramic body, an inner electrode, an outer electrode, and a connecting portion. The inner electrode is disposed inside the ceramic body. The end portion of the inner electrode extends to a surface of the ceramic body. The outer electrode is disposed on the surface of the ceramic body so as to cover the end portion of the inner electrode. The outer electrode includes a resin and a metal. The connecting portion is disposed so as to extend from an inside of the outer electrode to an inside of the ceramic body. In a portion of the surface of the ceramic body on which the outer electrode is disposed, the length of the connecting portion that extends in a direction in which the inner electrode is extends about 2.4 ?m or more.

Abstract: A semiconductor memory device is capable of executing a first mode having a first latency and a second mode having a second latency longer than the first latency. The semiconductor memory device includes: a pad unit configured to receive an address and a command from an outside; a first delay circuit configured to delay the address by a time corresponding to the first latency; a second delay circuit including shift registers connected in series and configured to delay the address by a time corresponding to a difference between the first latency and the second latency; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode.

Abstract: A ceramic electronic component includes a ceramic body, an inner electrode, an outer electrode, and a connecting portion. The inner electrode is disposed inside the ceramic body. The end portion of the inner electrode extends to a surface of the ceramic body. The outer electrode is disposed on the surface of the ceramic body so as to cover the end portion of the inner electrode. The outer electrode includes a resin and a metal. The connecting portion is disposed so as to extend from an inside of the outer electrode to an inside of the ceramic body. In a portion of the surface of the ceramic body on which the outer electrode is disposed, the length of the connecting portion that extends in a direction in which the inner electrode is extends about 2.4 ?m or more.

Abstract: A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows of each of the banks; an address latch circuit configured to latch a full address for specifying one of the word lines, the full address including a first address and a second address; and a control circuit configured to ignore a reset operation for the first address as a target of a set operation, and overwrite the first address in accordance with the set operation when receiving a first command for specifying a reset operation for a bank and a set operation for the first address.