Patents by Inventor Naoya Sashida

Naoya Sashida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180102373
    Abstract: A semiconductor device includes: a semiconductor substrate; a ferroelectric capacitor above the semiconductor substrate; a first guard ring around the ferroelectric capacitor above the semiconductor substrate. The ferroelectric capacitor includes a bottom electrode, a capacitor insulating film and a top electrode. The first guard ring includes a first pseudo bottom electrode, a first pseudo capacitor insulating film and a first pseudo top electrode, and surrounds the ferroelectric capacitors in planar view.
    Type: Application
    Filed: December 8, 2017
    Publication date: April 12, 2018
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Naoya SASHIDA, Tatsuya SUGIMACHI
  • Patent number: 9773794
    Abstract: An embodiment of a semiconductor device includes a plate line that is connected to ferroelectric capacitors selected from a plurality of ferroelectric capacitors and covers the selected ferroelectric capacitors and regions between the selected ferroelectric capacitors from above top electrodes.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: September 26, 2017
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Naoya Sashida
  • Patent number: 9508559
    Abstract: A semiconductor wafer including patterns transferred to a plurality of shot regions of the semiconductor wafer respectively, a plurality of chip regions being formed in the plurality of shot regions respectively, a plurality of first dummy patterns being formed respectively in a first chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of first dummy patterns being arranged repeatedly in a first manner, a plurality of second dummy patterns being formed respectively in a second chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of second dummy patterns being arranged repeatedly in a second manner different from the first manner.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: November 29, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shoko Saito, Tomoyuki Okada, Kanji Takeuchi, Mitsufumi Naoe, Masahiko Minemura, Yukihiro Sato, Yoshito Konno, Yasuhiko Inada, Tomoaki Inaoka, Naoya Sashida
  • Publication number: 20160268272
    Abstract: An embodiment of a semiconductor device includes a plate line that is connected to ferroelectric capacitors selected from a plurality of ferroelectric capacitors and covers the selected ferroelectric capacitors and regions between the selected ferroelectric capacitors from above top electrodes.
    Type: Application
    Filed: May 24, 2016
    Publication date: September 15, 2016
    Inventor: Naoya Sashida
  • Patent number: 9373626
    Abstract: An embodiment of a semiconductor device includes a plate line that is connected to ferroelectric capacitors selected from a plurality of ferroelectric capacitors and covers the selected ferroelectric capacitors and regions between the selected ferroelectric capacitors from above top electrodes.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: June 21, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Naoya Sashida
  • Publication number: 20160093627
    Abstract: A semiconductor device includes: a semiconductor substrate; a ferroelectric capacitor above the semiconductor substrate; a first guard ring around the ferroelectric capacitor above the semiconductor substrate. The ferroelectric capacitor includes a bottom electrode, a capacitor insulating film and a top electrode. The first guard ring includes a first pseudo bottom electrode, a first pseudo capacitor insulating film and a first pseudo top electrode, and surrounds the ferroelectric capacitors in planar view.
    Type: Application
    Filed: August 20, 2015
    Publication date: March 31, 2016
    Inventors: Naoya SASHIDA, TATSUYA SUGIMACHI
  • Publication number: 20150221657
    Abstract: An embodiment of a semiconductor device includes a plate line that is connected to ferroelectric capacitors selected from a plurality of ferroelectric capacitors and covers the selected ferroelectric capacitors and regions between the selected ferroelectric capacitors from above top electrodes.
    Type: Application
    Filed: January 21, 2015
    Publication date: August 6, 2015
    Inventor: Naoya Sashida
  • Patent number: 8815612
    Abstract: A ferroelectric memory device includes a field effect transistor formed on a semiconductor substrate, an interlayer insulation film formed on the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug, wherein the ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below, the lower electrode being connected electrically to the conductive plug, a layer containing oxygen being interposed between the conductive plug and the lower electrode, a layer containing nitrogen being interposed between the layer containing oxygen and the lower electrode, a self-aligned layer being interposed between the layer containing nitrogen and the lower electrode.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: August 26, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Patent number: 8772847
    Abstract: A semiconductor device includes a semiconductor substrate; a first insulating film that is formed over the semiconductor substrate; a capacitor that is formed over the first insulating film and is formed by sequentially stacking a lower electrode, a capacitor dielectric film, and an upper electrode; a second insulating film that is formed over the capacitor and has a hole including the entire region of the upper electrode in plan view; and a conductor plug that is formed in the hole and contains tungsten.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: July 8, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Patent number: 8735954
    Abstract: A semiconductor device includes a semiconductor substrate; a first insulating film that is formed over the semiconductor substrate; a capacitor that is formed over the first insulating film and is formed by sequentially stacking a lower electrode, a capacitor dielectric film, and an upper electrode; a second insulating film that is formed over the capacitor and has a hole including the entire region of the upper electrode in plan view; and a conductor plug that is formed in the hole and contains tungsten.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: May 27, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Publication number: 20140110712
    Abstract: A semiconductor wafer including patterns transferred to a plurality of shot regions of the semiconductor wafer respectively, a plurality of chip regions being formed in the plurality of shot regions respectively, a plurality of first dummy patterns being formed respectively in a first chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of first dummy patterns being arranged repeatedly in a first manner, a plurality of second dummy patterns being formed respectively in a second chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of second dummy patterns being arranged repeatedly in a second manner different from the first manner.
    Type: Application
    Filed: September 18, 2013
    Publication date: April 24, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shoko Saito, Tomoyuki Okada, Kanji Takeuchi, MITSUFUMI NAOE, Masahiko Minemura, Yukihiro Sato, Yoshito Konno, Yasuhiko Inada, Tomoaki Inaoka, Naoya SASHIDA
  • Publication number: 20130295693
    Abstract: A semiconductor device with a functional element including an upper electrode composed of an electrically conductive metal oxide and being configured to store information; an interlayer insulating film covering the functional element; a contact hole formed in the interlayer insulating film, the contact hole including a side wall surface and a bottom and exposing an upper surface of the upper electrode at the bottom; an electrically conductive barrier film covering the bottom and the side wall surface of the contact hole; and a tungsten film formed on the electrically conductive barrier film, the tungsten film filling at least part of the contact hole, wherein a layer in which silicon atoms are concentrated is formed at the interface between the tungsten film and the electrically conductive barrier film.
    Type: Application
    Filed: June 28, 2013
    Publication date: November 7, 2013
    Inventor: Naoya Sashida
  • Patent number: 8558294
    Abstract: A semiconductor device includes a semiconductor substrate formed with an active element, an oxidation resistant film formed over the semiconductor substrate so as to cover the active element, a ferroelectric capacitor formed over the oxidation resistance film, the ferroelectric capacitor having a construction of consecutively stacking a lower electrode, a ferroelectric film and an upper electrode, and an interlayer insulation film formed over the oxidation resistance film so as to cover the ferroelectric capacitor, wherein there are formed, in the interlayer insulation film, a first via-plug in a first contact hole exposing the first electrode and a second via-plug in a second contact hole exposing the lower electrode, and wherein there is formed another conductive plug in the interlayer insulation film in an opening exposing the oxidation resistant film.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: October 15, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Patent number: 8507965
    Abstract: An insulation film (24) having a gradual inclination of a surface is formed by a high density plasma CVD method, an atmospheric pressure CVD method or the like, after a ferroelectric capacitor (23) is formed. Thereafter, an alumina film (25) is formed on the insulation film (24). According to the method, low coverage of the alumina film (25) does not become a problem, and the ferroelectric capacitor (23) is reliably protected.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: August 13, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazutoshi Izumi, Hitoshi Saito, Naoya Sashida, Kaoru Saigoh, Kouichi Nagai
  • Patent number: 8354701
    Abstract: A method for fabricating a ferroelectric memory device, including terminating a surface of the interlayer insulation film and a surface of the contact plug with an OH group; forming a layer containing Si, oxygen and a CH group on the surface of the interlayer insulation film and the contact hole terminated with the OH group by coating a Si compound containing a Si atom and a CH group in a molecule thereof; converting the layer containing Si, oxygen and the CH group to a layer containing nitrogen at a surface thereof, by substituting the CH group in the layer containing Si, oxygen and the CH group at least at a surface part thereof with nitrogen atoms; and forming a layer showing self-orientation on the surface containing nitrogen.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: January 15, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Publication number: 20120309112
    Abstract: A ferroelectric memory device includes a field effect transistor formed on a semiconductor substrate, an interlayer insulation film formed on the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug, wherein the ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below, the lower electrode being connected electrically to the conductive plug, a layer containing oxygen being interposed between the conductive plug and the lower electrode, a layer containing nitrogen being interposed between the layer containing oxygen and the lower electrode, a self-aligned layer being interposed between the layer containing nitrogen and the lower electrode.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 6, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Naoya Sashida
  • Patent number: 8216857
    Abstract: A ferroelectric memory device includes a field effect transistor formed on a semiconductor substrate, an interlayer insulation film formed on the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug, wherein the ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below, the lower electrode being connected electrically to the conductive plug, a layer containing oxygen being interposed between the conductive plug and the lower electrode, a layer containing nitrogen being interposed between the layer containing oxygen and the lower electrode, a self-aligned layer being interposed between the layer containing nitrogen and the lower electrode.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: July 10, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Publication number: 20120107965
    Abstract: A semiconductor device includes an insulating film provided over a semiconductor substrate, a conductive plug buried in the insulating film, an underlying conductive film which is provided on the conductive plug and on the insulating film and which has a flat upper surface, and a ferroelectric capacitor provided on the underlying conductive film. At least in a region on the conductive plug, the concentration of nitrogen in the underlying conductive film gradually decreases from the upper surface to the inside.
    Type: Application
    Filed: January 9, 2012
    Publication date: May 3, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Naoya Sashida
  • Patent number: 8120087
    Abstract: A semiconductor device includes an insulating film provided over a semiconductor substrate, a conductive plug buried in the insulating film, an underlying conductive film which is provided on the conductive plug and on the insulating film and which has a flat upper surface, and a ferroelectric capacitor provided on the underlying conductive film. At least in a region on the conductive plug, the concentration of nitrogen in the underlying conductive film gradually decreases from the upper surface to the inside.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: February 21, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Patent number: 7893472
    Abstract: A ferroelectric memory device manufacturing method includes the steps of forming an interlayer isolating film for covering a transistor formed on a semiconductor substrate; forming a conductive plug in the interlayer insulating film to contact a diffusion region of the transistor formed on the semiconductor substrate; forming a ferroelectric capacitor including a lower electrode, a ferroelectric film and an upper electrode; and forming a compound film including silicon (Si) and a CH group on a surface of the interlayer insulating film and a surface of the conductive plug by depositing a Si compound containing Si atoms and the CH groups; wherein the compound film is formed after forming the conductive plug, and the compound film is formed before forming the lower electrode; and a self-orientation film is formed on a surface of the compound film.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: February 22, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Naoya Sashida, Katsuyoshi Matsuura