Patents by Inventor Naoya Sashida

Naoya Sashida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7528432
    Abstract: There is provided a semiconductor device manufacturing method which comprises the steps of forming a first insulating film over a silicon substrate (semiconductor substrate), forming a lower electrode, a dielectric film, and an upper electrode of a capacitor on the first insulating film, forming a first capacitor protection insulating film for covering at least the dielectric film and the upper electrode, forming a second capacitor protection insulating film, which covers the first capacitor protection insulating film, by a chemical vapor deposition method in a state that a bias voltage is not applied to the silicon substrate, and forming a second insulating film on the second capacitor protection insulating film by the chemical vapor deposition method in a state that the bias voltage is applied to the silicon substrate.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: May 5, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Naoya Sashida
  • Patent number: 7518173
    Abstract: A semiconductor device includes: a semiconductor substrate; a MOS transistor formed in the semiconductor substrate and having an insulated gate and source/drain regions on both sides of the insulated gate; a ferroelectric capacitor formed above the semiconductor substrate and having a lower electrode, a ferroelectric layer and an upper electrode; a metal film formed on the upper electrode and having a thickness of a half of or thinner than a thickness of the upper electrode; an interlayer insulating film burying the ferroelectric capacitor and the metal film; a conductive plug formed through the interlayer insulating film, reaching the metal film and including a conductive glue film and a tungsten body; and an aluminum wiring formed on the interlayer insulating film and connected to the conductive plug. A new problem near an upper electrode contact is solved which may otherwise be caused by adopting a W plug over the F capacitor.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: April 14, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Yukinobu Hikosaka, Mitsushi Fujiki, Kazutoshi Izumi, Naoya Sashida, Aki Dote
  • Publication number: 20090068764
    Abstract: According to the present invention, contact plugs are formed by a CVD method without deteriorating the properties of the ferroelectric capacitor in a semiconductor device having a fine ferroelectric capacitor. Adhesive film is formed in a contact hole, which exposes an upper electrode of the ferroelectric capacitor after conducting heat treatment in an oxidizing atmosphere, and a W layer is deposited by the CVD method using such TiN adhesive film as a hydrogen barrier and the contact hole is filled.
    Type: Application
    Filed: October 14, 2008
    Publication date: March 12, 2009
    Applicant: FUJITSU LIMITED
    Inventor: Naoya Sashida
  • Patent number: 7501325
    Abstract: The method for fabricating the semiconductor device comprises: the step of forming a ferroelectric capacitor over a semiconductor substrate 10; the step of forming an insulating film 54, covering the ferroelectric capacitor; the step of processing thermal treatment to eliminate hydrogen and/or water adsorbed on a surface of the insulating film 54 or occluded in the insulating film 54; and the step of forming a capacitor protective film 56 of an aluminum oxide film over the insulating film 54. The step of processing the thermal treatment and the step of forming the capacitor protective film are performed continuously in the same system without exposing to an ambient atmosphere.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: March 10, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Katsuyoshi Matsuura, Naoya Sashida
  • Patent number: 7476921
    Abstract: There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: January 13, 2009
    Assignee: Fujitsu Limited
    Inventor: Naoya Sashida
  • Patent number: 7473980
    Abstract: The semiconductor device comprises a capacitor formed over a semiconductor substrate 10 and including a lower electrode 32, a dielectric film 34 formed over the lower electrode and an upper electrode 36 formed over the dielectric film, a first insulation film 42 formed over the semiconductor substrate and the capacitor, a first interconnection 48 formed over the first insulation film and electrically connected to the capacitor, a first hydrogen diffusion preventive film 50 for preventing the diffusion of hydrogen formed over the first insulation film, covering the first interconnection, a second insulation film 58 formed over the first hydrogen diffusion preventive film and having the surface planarized, a third insulation film 62 formed over the second insulation film, a second interconnection 70b formed over the third insulation film, and a second hydrogen diffusion preventive film 72 for preventing the diffusion of hydrogen formed on the third insulation film, covering the second interconnection.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: January 6, 2009
    Assignee: Fujitsu Limited
    Inventors: Naoya Sashida, Tatsuya Yokota
  • Patent number: 7456454
    Abstract: According to the present invention, contact plugs are formed by a CVD method without deteriorating the properties of the ferroelectric capacitor in a semiconductor device having a fine ferroelectric capacitor. Adhesive film is formed in a contact hole, which exposes an upper electrode of the ferroelectric capacitor after conducting heat treatment in an oxidizing atmosphere, and a W layer is deposited by the CVD method using such TiN adhesive film as a hydrogen barrier and the contact hole is filled.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: November 25, 2008
    Assignee: Fujitsu Limited
    Inventor: Naoya Sashida
  • Publication number: 20080277706
    Abstract: A ferroelectric memory device manufacturing method includes the steps of forming an interlayer isolating film for covering a transistor formed on a semiconductor substrate; forming a conductive plug in the interlayer insulating film to contact a diffusion region of the transistor formed on the semiconductor substrate; forming a ferroelectric capacitor including a lower electrode, a ferroelectric film and an upper electrode; and forming a compound film including silicon (Si) and a CH group on a surface of the interlayer insulating film and a surface of the conductive plug by depositing a Si compound containing Si atoms and the CH groups; wherein the compound film is formed after forming the conductive plug, and the compound film is formed before forming the lower electrode; and a self-orientation film is formed on a surface of the compound film.
    Type: Application
    Filed: July 22, 2008
    Publication date: November 13, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Naoya SASHIDA, Katsuyoshi MATSUURA
  • Publication number: 20080224194
    Abstract: A semiconductor device includes a semiconductor substrate formed with an active element, an oxidation resistant film formed over the semiconductor substrate so as to cover the active element, a ferroelectric capacitor formed over the oxidation resistance film, the ferroelectric capacitor having a construction of consecutively stacking a lower electrode, a ferroelectric film and an upper electrode, and an interlayer insulation film formed over the oxidation resistance film so as to cover the ferroelectric capacitor, wherein there are formed, in the interlayer insulation film, a first via-plug in a first contact hole exposing the first electrode and a second via-plug in a second contact hole exposing the lower electrode, and wherein there is formed another conductive plug in the interlayer insulation film in an opening exposing the oxidation resistant film.
    Type: Application
    Filed: May 23, 2008
    Publication date: September 18, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Naoya Sashida
  • Publication number: 20080185623
    Abstract: A method for fabricating a ferroelectric memory device, including terminating a surface of the interlayer insulation film and a surface of the contact plug with an OH group; forming a layer containing Si, oxygen and a CH group on the surface of the interlayer insulation film and the contact hole terminated with the OH group by coating a Si compound containing a Si atom and a CH group in a molecule thereof; converting the layer containing Si, oxygen and the CH group to a layer containing nitrogen at a surface thereof, by substituting the CH group in the layer containing Si, oxygen and the CH group at least at a surface part thereof with nitrogen atoms; and forming a layer showing self-orientation on the surface containing nitrogen.
    Type: Application
    Filed: April 2, 2008
    Publication date: August 7, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Naoya SASHIDA
  • Publication number: 20080142915
    Abstract: A ferroelectric memory device includes a field effect transistor formed over a semiconductor substrate and including first and second diffusion regions, an interlayer insulation film formed over the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug. The ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below.
    Type: Application
    Filed: February 26, 2008
    Publication date: June 19, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Naoya Sashida
  • Publication number: 20080145954
    Abstract: A manufacturing method for a ferroelectric memory device includes: forming a ferroelectric capacitor on a substrate, the ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode; forming a first hydrogen barrier film that covers the ferroelectric capacitor by a chemical vapor deposition method; forming a dielectric film on the first hydrogen barrier film; forming a sidewall composed of the dielectric film on a side of the ferroelectric capacitor by etching back the dielectric film; forming a second hydrogen barrier film on the first hydrogen barrier film and the sidewall by a chemical vapor deposition method; and forming an interlayer dielectric film on the second hydrogen barrier film.
    Type: Application
    Filed: November 28, 2007
    Publication date: June 19, 2008
    Inventors: Shinichi Fukada, Naoya Sashida
  • Publication number: 20080054402
    Abstract: There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.
    Type: Application
    Filed: September 18, 2007
    Publication date: March 6, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Naoya SASHIDA
  • Patent number: 7285460
    Abstract: There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: October 23, 2007
    Assignee: Fujitsu Limited
    Inventor: Naoya Sashida
  • Publication number: 20070063241
    Abstract: The semiconductor device comprises a capacitor formed over a semiconductor substrate 10 and including a lower electrode 32, a dielectric film 34 formed over the lower electrode and an upper electrode 36 formed over the dielectric film, a first insulation film 42 formed over the semiconductor substrate and the capacitor, a first interconnection 48 formed over the first insulation film and electrically connected to the capacitor, a first hydrogen diffusion preventive film 50 for preventing the diffusion of hydrogen formed over the first insulation film, covering the first interconnection, a second insulation film 58 formed over the first hydrogen diffusion preventive film and having the surface planarized, a third insulation film 62 formed over the second insulation film, a second interconnection 70b formed over the third insulation film, and a second hydrogen diffusion preventive film 72 for preventing the diffusion of hydrogen formed on the third insulation film, covering the second interconnection.
    Type: Application
    Filed: October 2, 2006
    Publication date: March 22, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Naoya Sashida, Tatsuya Yokota
  • Publication number: 20070063239
    Abstract: A semiconductor device includes: a substrate; a first insulating layer formed on the substrate; a groove formed in the first insulating layer; a barrier layer formed on at least a side surface and a bottom surface of the groove; a second insulating layer formed on the barrier layer; a first electrode formed on at least the barrier layer and the second insulating layer; a ferroelectric layer formed over the first electrode; and a second electrode formed over the ferroelectric layer.
    Type: Application
    Filed: September 18, 2006
    Publication date: March 22, 2007
    Inventors: Kenji Yamada, Naoya Sashida
  • Publication number: 20070045688
    Abstract: A ferroelectric memory device includes a field effect transistor formed on a semiconductor substrate, an interlayer insulation film formed on the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug, wherein the ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below, the lower electrode being connected electrically to the conductive plug, a layer containing oxygen being interposed between the conductive plug and the lower electrode, a layer containing nitrogen being interposed between the layer containing oxygen and the lower electrode, a self-aligned layer being interposed between the layer containing nitrogen and the lower electrode.
    Type: Application
    Filed: December 23, 2005
    Publication date: March 1, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Naoya Sashida
  • Patent number: 7176132
    Abstract: There are provided a step of forming an insulating film over a semiconductor substrate, a step of exciting a plasma of a gas having a molecular structure in which hydrogen and nitrogen are bonded and then irradiating the plasma onto the insulating film, a step of forming a self-orientation layer made of substance having a self-orientation characteristic on the insulating film, and a step of forming a first conductive film made of conductive substance having the self-orientation characteristic on the self-orientation layer.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: February 13, 2007
    Assignee: Fujitsu Limited
    Inventors: Naoya Sashida, Katsuyoshi Matsuura, Yoshimasa Horii, Masaki Kurasawa, Kazuaki Takai
  • Publication number: 20070032015
    Abstract: To provide a semiconductor device capable of improving accuracy in finishing a hole in which a conductive plug right under a capacitor, and a manufacturing method of such a semiconductor device comprising the following steps: a step of forming first and second conductive plugs 32a, 32b in first and second holes 11a, 11b in a first insulating film 11; a step of forming a first opening 14a in an oxidation preventing insulating film 14; a step of forming an auxiliary conductive plug 36a in the first opening 14a; a step of forming a capacitor Q on the auxiliary conductive plug 36a; a step of forming third and fourth holes 41a, 41b in a second insulating film 41 covering the capacitor Q; a step of forming the second opening 14b in the oxidation preventing insulating film 14 under the fourth hole 41b; a step of forming a third conductive plug 47a in the third hole 41a; and a step of forming a fourth conductive plug 47b in the third hole 41a.
    Type: Application
    Filed: January 6, 2006
    Publication date: February 8, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Akio Itoh, Naoya Sashida
  • Patent number: 7153735
    Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first insulating film 9, 10 above a semiconductor substrate 1; forming a capacitor Q having a lower electrode 11a, a dielectric film 13a, and an upper electrode 14c on the first insulating film 9, 10; forming a second insulating film 15, 15a, 16 coating the capacitor Q; and forming a stress-controlling insulating film 30 on the rear surface of the semiconductor substrate 1 after the second insulating film 15, 15a, 16 have been formed.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: December 26, 2006
    Assignee: Fujitsu Limited
    Inventor: Naoya Sashida