Patents by Inventor Naoya Sashida

Naoya Sashida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7884404
    Abstract: A ferroelectric memory device includes a field effect transistor formed over a semiconductor substrate and including first and second diffusion regions, an interlayer insulation film formed over the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug. The ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: February 8, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Publication number: 20110012230
    Abstract: An insulation film (24) having a gradual inclination of a surface is formed by a high density plasma CVD method, an atmospheric pressure CVD method or the like, after a ferroelectric capacitor (23) is formed. Thereafter, an alumina film (25) is formed on the insulation film (24). According to the method, low coverage of the alumina film (25) does not become a problem, and the ferroelectric capacitor (23) is reliably protected.
    Type: Application
    Filed: October 1, 2010
    Publication date: January 20, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazutoshi Izumi, Hitoshi Saito, Naoya Sashida, Kaoru Saigoh, Kouichi Nagai
  • Publication number: 20100301436
    Abstract: A semiconductor device with a functional element including an upper electrode composed of an electrically conductive metal oxide and being configured to store information; an interlayer insulating film covering the functional element; a contact hole formed in the interlayer insulating film, the contact hole including a side wall surface and a bottom and exposing an upper surface of the upper electrode at the bottom; an electrically conductive barrier film covering the bottom and the side wall surface of the contact hole; and a tungsten film formed on the electrically conductive barrier film, the tungsten film filling at least part of the contact hole, wherein a layer in which silicon atoms are concentrated is formed at the interface between the tungsten film and the electrically conductive barrier film.
    Type: Application
    Filed: May 24, 2010
    Publication date: December 2, 2010
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Naoya Sashida
  • Publication number: 20100295108
    Abstract: A method for fabricating a ferroelectric memory device, including terminating a surface of the interlayer insulation film and a surface of the contact plug with an OH group; forming a layer containing Si, oxygen and a CH group on the surface of the interlayer insulation film and the contact hole terminated with the OH group by coating a Si compound containing a Si atom and a CH group in a molecule thereof; converting the layer containing Si, oxygen and the CH group to a layer containing nitrogen at a surface thereof, by substituting the CH group in the layer containing Si, oxygen and the CH group at least at a surface part thereof with nitrogen atoms; and forming a layer showing self-orientation on the surface containing nitrogen.
    Type: Application
    Filed: July 30, 2010
    Publication date: November 25, 2010
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Naoya SASHIDA
  • Patent number: 7790476
    Abstract: A method for fabricating a ferroelectric memory device, including terminating a surface of the interlayer insulation film and a surface of the contact plug with an OH group; forming a layer containing Si, oxygen and a CH group on the surface of the interlayer insulation film and the contact hole terminated with the OH group by coating a Si compound containing a Si atom and a CH group in a molecule thereof; converting the layer containing Si, oxygen and the CH group to a layer containing nitrogen at a surface thereof, by substituting the CH group in the layer containing Si, oxygen and the CH group at least at a surface part thereof with nitrogen atoms; and forming a layer showing self-orientation on the surface containing nitrogen.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: September 7, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Patent number: 7781284
    Abstract: There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: August 24, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Patent number: 7745232
    Abstract: According to the present invention, contact plugs are formed by a CVD method without deteriorating the properties of the ferroelectric capacitor in a semiconductor device having a fine ferroelectric capacitor. Adhesive film is formed in a contact hole, which exposes an upper electrode of the ferroelectric capacitor after conducting heat treatment in an oxidizing atmosphere, and a W layer is deposited by the CVD method using such TiN adhesive film as a hydrogen barrier and the contact hole is filled.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: June 29, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Publication number: 20100140743
    Abstract: There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.
    Type: Application
    Filed: February 16, 2010
    Publication date: June 10, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Naoya SASHIDA
  • Patent number: 7678646
    Abstract: To provide a semiconductor device capable of improving accuracy in finishing a hole in which a conductive plug right under a capacitor, and a manufacturing method of such a semiconductor device comprising the following steps: a step of forming first and second conductive plugs 32a, 32b in first and second holes 11a, 11b in a first insulating film 11; a step of forming a first opening 14a in an oxidation preventing insulating film 14; a step of forming an auxiliary conductive plug 36a in the first opening 14a; a step of forming a capacitor Q on the auxiliary conductive plug 36a; a step of forming third and fourth holes 41a, 41b in a second insulating film 41 covering the capacitor Q; a step of forming the second opening 14b in the oxidation preventing insulating film 14 under the fourth hole 41b; a step of forming a third conductive plug 47a in the third hole 41a; and a step of forming a fourth conductive plug 47b in the third hole 41a.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: March 16, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Akio Itoh, Naoya Sashida
  • Patent number: 7655531
    Abstract: The semiconductor device comprises a capacitor formed over a semiconductor substrate 10 and including a lower electrode 32, a dielectric film 34 formed over the lower electrode and an upper electrode 36 formed over the dielectric film, a first insulation film 42 formed over the semiconductor substrate and the capacitor, a first interconnection 48 formed over the first insulation film and electrically connected to the capacitor, a first hydrogen diffusion preventive film 50 for preventing the diffusion of hydrogen formed over the first insulation film, covering the first interconnection, a second insulation film 58 formed over the first hydrogen diffusion preventive film and having the surface planarized, a third insulation film 62 formed over the second insulation film, a second interconnection 70b formed over the third insulation film, and a second hydrogen diffusion preventive film 72 for preventing the diffusion of hydrogen formed on the third insulation film, covering the second interconnection.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: February 2, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Naoya Sashida, Tatsuya Yokota
  • Publication number: 20100001325
    Abstract: A semiconductor device includes an insulating film provided over a semiconductor substrate, a conductive plug buried in the insulating film, an underlying conductive film which is provided on the conductive plug and on the insulating film and which has a flat upper surface, and a ferroelectric capacitor provided on the underlying conductive film. At least in a region on the conductive plug, the concentration of nitrogen in the underlying conductive film gradually decreases from the upper surface to the inside.
    Type: Application
    Filed: June 30, 2009
    Publication date: January 7, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Naoya Sashida
  • Patent number: 7642099
    Abstract: A manufacturing method for a ferroelectric memory device includes: forming a ferroelectric capacitor on a substrate, the ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode; forming a first hydrogen barrier film that covers the ferroelectric capacitor by a chemical vapor deposition method; forming a dielectric film on the first hydrogen barrier film; forming a sidewall composed of the dielectric film on a side of the ferroelectric capacitor by etching back the dielectric film; forming a second hydrogen barrier film on the first hydrogen barrier film and the sidewall by a chemical vapor deposition method; and forming an interlayer dielectric film on the second hydrogen barrier film.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: January 5, 2010
    Assignees: Seiko Epson Corporation, Fujtisu Limited
    Inventors: Shinichi Fukada, Naoya Sashida
  • Publication number: 20090280578
    Abstract: A ferroelectric memory device includes a field effect transistor formed on a semiconductor substrate, an interlayer insulation film formed on the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug, wherein the ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below, the lower electrode being connected electrically to the conductive plug, a layer containing oxygen being interposed between the conductive plug and the lower electrode, a layer containing nitrogen being interposed between the layer containing oxygen and the lower electrode, a self-aligned layer being interposed between the layer containing nitrogen and the lower electrode.
    Type: Application
    Filed: July 14, 2009
    Publication date: November 12, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Naoya SASHIDA
  • Publication number: 20090278231
    Abstract: The semiconductor device comprises a first insulation film 26 formed over a semiconductor substrate 10, first conductor plug 32 buried in a first contact hole 28a formed down to a source/drain diffused layer 22, a capacitor 44 formed over the first insulation film 26, a first hydrogen diffusion preventing film 48 formed over the first insulation film 26, covering the capacitor 44, a second insulation film 50 formed over the first hydrogen diffusion preventing film and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the first hydrogen diffusion preventing film 26 and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the second insulation film 50, second conductor plug 62 buried in a second contact hole 56 formed down to the lower electrode 38 or the upper electrode 42 of the capacitor 44, a third conductor plug 62 buried in a third contact hole 58 formed down to the first conductor plug 32, and an interconnection 64 connected to
    Type: Application
    Filed: July 14, 2009
    Publication date: November 12, 2009
    Applicant: Fujitsu Microelectronics Limited
    Inventors: Kouichi Nagai, Hideaki Kikuchi, Naoya Sashida, Yasutaka Ozaki
  • Patent number: 7598557
    Abstract: The semiconductor device comprises a first insulation film 26 formed over a semiconductor substrate 10, first conductor plug 32 buried in a first contact hole 28a formed down to a source/drain diffused layer 22, a capacitor 44 formed over the first insulation film 26, a first hydrogen diffusion preventing film 48 formed over the first insulation film 26, covering the capacitor 44, a second insulation film 50 formed over the first hydrogen diffusion preventing film and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the first hydrogen diffusion preventing film 26 and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the second insulation film 50, second conductor plug 62 buried in a second contact hole 56 formed down to the lower electrode 38 or the upper electrode 42 of the capacitor 44, a third conductor plug 62 buried in a third contact hole 58 formed down to the first conductor plug 32, and an interconnection 64 connected to
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: October 6, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Kouichi Nagai, Hideaki Kikuchi, Naoya Sashida, Yasutaka Ozaki
  • Patent number: 7579641
    Abstract: A ferroelectric memory device includes a field effect transistor formed on a semiconductor substrate, an interlayer insulation film formed on the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug, wherein the ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below, the lower electrode being connected electrically to the conductive plug, a layer containing oxygen being interposed between the conductive plug and the lower electrode, a layer containing nitrogen being interposed between the layer containing oxygen and the lower electrode, a self-aligned layer being interposed between the layer containing nitrogen and the lower electrode.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: August 25, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Naoya Sashida
  • Publication number: 20090160023
    Abstract: An insulation film (24) having a gradual inclination of a surface is formed by a high density plasma CVD method, an atmospheric pressure CVD method or the like, after a ferroelectric capacitor (23) is formed. Thereafter, an alumina film (25) is formed on the insulation film (24). According to the method, low coverage of the alumina film (25) does not become a problem, and the ferroelectric capacitor (23) is reliably protected.
    Type: Application
    Filed: February 24, 2009
    Publication date: June 25, 2009
    Applicant: Fujitsu Microelectronics Limited
    Inventors: Kazutoshi Izumi, Hitoshi Saito, Naoya Sashida, Kaoru Saigoh, Kouichi Nagai
  • Patent number: 7547558
    Abstract: An Al2O3 film for covering a ferroelectric capacitor is formed by a sputtering process. The thickness of the Al2O3 film is preferably optimized according to amount of remanent polarization and fatigue tolerance required for the ferroelectric capacitor, for example, 10 nm to 100 nm. Next, oxygen is supplied to a PZT film via the Al2O3 film by executing a heat treatment in an oxygen atmosphere. As a result, an oxygen deficit in the PZT film is made up for. At this time, evaporation of Pb in the PZT film is suppressed because of the Al2O3 film, and deterioration of the fatigue tolerance responsive to decrease of Pb amount is suppressed. Subsequently, another Al2O3 film is formed as a second protective film by the sputtering process for opposing the deterioration factor in later process. The thickness of the Al2O3 film is preferably the thickness which sufficiently protects the ferroelectric capacitor from the deterioration factor in later wiring process.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: June 16, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Yoichi Okita, Junichi Watanabe, Naoya Sashida
  • Publication number: 20090130815
    Abstract: The semiconductor device comprises a capacitor formed over a semiconductor substrate 10 and including a lower electrode 32, a dielectric film 34 formed over the lower electrode and an upper electrode 36 formed over the dielectric film, a first insulation film 42 formed over the semiconductor substrate and the capacitor, a first interconnection 48 formed over the first insulation film and electrically connected to the capacitor, a first hydrogen diffusion preventive film 50 for preventing the diffusion of hydrogen formed over the first insulation film, covering the first interconnection, a second insulation film 58 formed over the first hydrogen diffusion preventive film and having the surface planarized, a third insulation film 62 formed over the second insulation film, a second interconnection 70b formed over the third insulation film, and a second hydrogen diffusion preventive film 72 for preventing the diffusion of hydrogen formed on the third insulation film, covering the second interconnection.
    Type: Application
    Filed: December 2, 2008
    Publication date: May 21, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Naoya Sashida, Tatsuya Yokota
  • Publication number: 20090127657
    Abstract: There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.
    Type: Application
    Filed: December 3, 2008
    Publication date: May 21, 2009
    Applicant: FUJITSU LIMITED
    Inventor: Naoya Sashida