Patents by Inventor Naoya Sashida
Naoya Sashida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060199342Abstract: The method for fabricating the semiconductor device comprises: the step of forming a ferroelectric capacitor over a semiconductor substrate 10; the step of forming an insulating film 54, covering the ferroelectric capacitor; the step of processing thermal treatment to eliminate hydrogen and/or water adsorbed on a surface of the insulating film 54 or occluded in the insulating film 54; and the step of forming a capacitor protective film 56 of an aluminum oxide film over the insulating film 54. The step of processing the thermal treatment and the step of forming the capacitor protective film are performed continuously in the same system without exposing to an ambient atmosphere.Type: ApplicationFiled: June 27, 2005Publication date: September 7, 2006Applicant: FUJITSU LIMITEDInventors: Katsuyoshi Matsuura, Naoya Sashida
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Publication number: 20060157762Abstract: A semiconductor device includes: a semiconductor substrate; a MOS transistor formed in the semiconductor substrate and having an insulated gate and source/drain regions on both sides of the insulated gate; a ferroelectric capacitor formed above the semiconductor substrate and having a lower electrode, a ferroelectric layer and an upper electrode; a metal film formed on the upper electrode and having a thickness of a half of or thinner than a thickness of the upper electrode; an interlayer insulating film burying the ferroelectric capacitor and the metal film; a conductive plug formed through the interlayer insulating film, reaching the metal film and including a conductive glue film and a tungsten body; and an aluminum wiring formed on the interlayer insulating film and connected to the conductive plug. A new problem near an upper electrode contact is solved which may otherwise be caused by adopting a W plug over the F capacitor.Type: ApplicationFiled: May 16, 2005Publication date: July 20, 2006Applicant: FUJITSU LIMITEDInventors: Yukinobu Hikosaka, Mitsushi Fujiki, Kazutoshi Izumi, Naoya Sashida, Aki Dote
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Publication number: 20060001026Abstract: There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.Type: ApplicationFiled: August 31, 2005Publication date: January 5, 2006Applicant: FUJITSU LIMITEDInventor: Naoya Sashida
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Publication number: 20050285173Abstract: The semiconductor device comprises a first insulation film 26 formed over a semiconductor substrate 10, first conductor plug 32 buried in a first contact hole 28a formed down to a source/drain diffused layer 22, a capacitor 44 formed over the first insulation film 26, a first hydrogen diffusion preventing film 48 formed over the first insulation film 26, covering the capacitor 44, a second insulation film 50 formed over the first hydrogen diffusion preventing film and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the first hydrogen diffusion preventing film 26 and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the second insulation film 50, second conductor plug 62 buried in a second contact hole 56 formed down to the lower electrode 38 or the upper electrode 42 of the capacitor 44, a third conductor plug 62 buried in a third contact hole 58 formed down to the first conductor plug 32, and an interconnection 64 connected toType: ApplicationFiled: January 27, 2005Publication date: December 29, 2005Applicant: FUJITSU LIMITEDInventors: Kouichi Nagai, Hideaki Kikuchi, Naoya Sashida, Yasutaka Ozaki
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Patent number: 6953950Abstract: There is provided a semiconductor device which includes a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.Type: GrantFiled: August 28, 2003Date of Patent: October 11, 2005Assignee: Fujitsu LimitedInventor: Naoya Sashida
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Publication number: 20050212020Abstract: An insulation film (24) having a gradual inclination of a surface is formed by a high density plasma CVD method, an atmospheric pressure CVD method or the like, after a ferroelectric capacitor (23) is formed. Thereafter, an alumina film (25) is formed on the insulation film (24). According to the method, low coverage of the alumina film (25) does not become a problem, and the ferroelectric capacitor (23) is reliably protected.Type: ApplicationFiled: May 20, 2005Publication date: September 29, 2005Applicant: FUJITSU LIMITEDInventors: Kazutoshi Izumi, Hitoshi Saito, Naoya Sashida, Kaoru Saigoh, Kouichi Nagai
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Publication number: 20050148139Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first insulating film 9, 10 above a semiconductor substrate 1; forming a capacitor Q having a lower electrode 11a, a dielectric film 13a, and an upper electrode 14c on the first insulating film 9, 10; forming a second insulating film 15, 15a, 16 coating the capacitor Q; and forming a stress-controlling insulating film 30 on the rear surface of the semiconductor substrate 1 after the second insulating film 15, 15a, 16 have been formed.Type: ApplicationFiled: February 3, 2005Publication date: July 7, 2005Applicant: FUJITSU LIMITEDInventor: Naoya Sashida
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Patent number: 6913970Abstract: A semiconductor device formed by forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.Type: GrantFiled: November 26, 2002Date of Patent: July 5, 2005Assignee: Fujitsu LimitedInventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki
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Publication number: 20050136554Abstract: An Al2O3 film for covering a ferroelectric capacitor is formed by a sputtering process. The thickness of the Al2O3 film is preferably optimized according to amount of remanent polarization and fatigue tolerance required for the ferroelectric capacitor, for example, 10 nm to 100 nm. Next, oxygen is supplied to a PZT film via the Al203 film by executing a heat treatment in an oxygen atmosphere. As a result, an oxygen deficit in the PZT film is made up for. At this time, evaporation of Pb in the PZT film is suppressed because of the Al2O3 film, and deterioration of the fatigue tolerance responsive to decrease of Pb amount is suppressed. Subsequently, another Al2O3 film is formed as a second protective film by the sputtering process for opposing the deterioration factor in later process. The thickness of the Al2O3 film is preferably the thickness which sufficiently protects the ferroelectric capacitor from the deterioration factor in later wiring process.Type: ApplicationFiled: April 30, 2004Publication date: June 23, 2005Applicant: FUJITSU LIMITEDInventors: Yoichi Okita, Junichi Watanabe, Naoya Sashida
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Patent number: 6872617Abstract: There are provided the steps of forming a first insulating film over a semiconductor substrate, forming a capacitor having a lower electrode, a ferroelectric layer, and an upper electrode over the first insulating film, and growing a second insulating film over the first insulating film and the capacitor by using a mixed gas containing a compound gas of oxygen and nitrogen, TEOS, and oxygen. Accordingly, characteristics of the capacitor can be improved irrespective of the capacitor forming position on the insulating layer.Type: GrantFiled: March 17, 2003Date of Patent: March 29, 2005Assignee: Fujitsu LimitedInventor: Naoya Sashida
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Publication number: 20040212041Abstract: There are provided a first insulating film over a semiconductor substrate, a capacitor formed on the first insulating film and having a lower electrode, a ferroelectric film, and an upper electrode, a capacitor-protection insulating film formed on the capacitor to apply a tensile stress of more than 2.0×109 dyn/cm2 to the capacitor, and a second insulating film formed on the capacitor-protection insulating film to apply a compressive stress of more than 2.6×109 dyn/cm2 to the capacitor.Type: ApplicationFiled: June 17, 2003Publication date: October 28, 2004Applicant: Fujitsu LimitedInventors: Tomohiro Takamatsu, Naoya Sashida, Naoyuki Sato
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Publication number: 20040166596Abstract: There are provided a step of forming an insulating film over a semiconductor substrate, a step of exciting a plasma of a gas having a molecular structure in which hydrogen and nitrogen are bonded and then irradiating the plasma onto the insulating film, a step of forming a self-orientation layer made of substance having a self-orientation characteristic on the insulating film, and a step of forming a first conductive film made of conductive substance having the self-orientation characteristic on the self-orientation layer.Type: ApplicationFiled: October 29, 2003Publication date: August 26, 2004Inventors: Naoya Sashida, Katsuyoshi Matsuura, Yoshimasa Horii, Masaki Kurasawa, Kazuaki Takai
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Publication number: 20040089894Abstract: There is provided a semiconductor device manufacturing method which comprises the steps of forming a first insulating film over a silicon substrate (semiconductor substrate), forming a lower electrode, a dielectric film, and an upper electrode of a capacitor on the first insulating film, forming a first capacitor protection insulating film for covering at least the dielectric film and the upper electrode, forming a second capacitor protection insulating film, which covers the first capacitor protection insulating film, by a chemical vapor deposition method in a state that a bias voltage is not applied to the silicon substrate, and forming a second insulating film on the second capacitor protection insulating film by the chemical vapor deposition method in a state that the bias voltage is applied to the silicon substrate.Type: ApplicationFiled: October 31, 2003Publication date: May 13, 2004Applicant: FUJITSU LIMITEDInventor: Naoya Sashida
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Publication number: 20040046185Abstract: There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.Type: ApplicationFiled: August 28, 2003Publication date: March 11, 2004Applicant: FUJITSU LIMITEDInventor: Naoya Sashida
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Publication number: 20040043517Abstract: There are provided the steps of forming a first insulating film over a semiconductor substrate, forming a capacitor having a lower electrode, a ferroelectric layer, and an upper electrode over the first insulating film, and growing a second insulating film over the first insulating film and the capacitor by using a mixed gas containing a compound gas of oxygen and nitrogen, TEOS, and oxygen. Accordingly, characteristics of the capacitor can be improved irrespective of the capacitor forming position on the insulating layer.Type: ApplicationFiled: March 17, 2003Publication date: March 4, 2004Applicant: Fujitsu LimitedInventor: Naoya Sashida
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Patent number: 6673672Abstract: There is provided a semiconductor device manufacturing method which comprises the steps of forming a first insulating film over a silicon substrate (semiconductor substrate), forming a lower electrode, a dielectric film, and an upper electrode of a capacitor on the first insulating film, forming a first capacitor protection insulating film for covering at least the dielectric film and the upper electrode, forming a second capacitor protection insulating film, which covers the first capacitor protection insulating film, by a chemical vapor deposition method in a state that a bias voltage is not applied to the silicon substrate, and forming a second insulating film on the second capacitor protection insulating film by the chemical vapor deposition method in a state that the bias voltage is applied to the silicon substrate.Type: GrantFiled: December 11, 2002Date of Patent: January 6, 2004Assignee: Fujitsu LimitedInventor: Naoya Sashida
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Publication number: 20030178663Abstract: There is provided a semiconductor device manufacturing method which comprises the steps of forming a first insulating film over a silicon substrate (semiconductor substrate), forming a lower electrode, a dielectric film, and an upper electrode of a capacitor on the first insulating film, forming a first capacitor protection insulating film for covering at least the dielectric film and the upper electrode, forming a second capacitor protection insulating film, which covers the first capacitor protection insulating film, by a chemical vapor deposition method in a state that a bias voltage is not applied to the silicon substrate, and forming a second insulating film on the second capacitor protection insulating film by the chemical vapor deposition method in a state that the bias voltage is applied to the silicon substrate.Type: ApplicationFiled: December 11, 2002Publication date: September 25, 2003Applicant: FUJITSU LIMITEDInventor: Naoya Sashida
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Publication number: 20030089954Abstract: According to the present invention, contact plugs are formed by a CVD method without deteriorating the properties of the ferroelectric capacitor in a semiconductor device having a fine ferroelectric capacitor. Adhesive film is formed in a contact hole, which exposes an upper electrode of the ferroelectric capacitor after conducting heat treatment in an oxidizing atmosphere, and a W layer is deposited by the CVD method using such TiN adhesive film as a hydrogen barrier and the contact hole is filled.Type: ApplicationFiled: March 14, 2002Publication date: May 15, 2003Applicant: Fujitsu LimitedInventor: Naoya Sashida
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Publication number: 20030080364Abstract: There are provided the steps of forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into the contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.Type: ApplicationFiled: November 26, 2002Publication date: May 1, 2003Applicant: Fujitsu LimitedInventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki
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Patent number: 6509593Abstract: A semiconductor device formed by forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into the contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.Type: GrantFiled: December 29, 2000Date of Patent: January 21, 2003Assignee: Fujitsu LimitedInventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki