Abstract: A dense wave division multiplex (DWDM) receiver includes receiver lanes each configured to detect signals encoded in a different electromagnetic frequency band. The DWDM receiver applies a clock signal received on a variable one of the receiver lanes to lock a frequency of an injection locked oscillator (ILO) of a clock distribution network, and receiver lanes that are configured to receive data signals generate resonance on the clock distribution network. The resonant signal from the clock distribution network is applied to sample the received data signals.

Abstract: Mechanisms for tuning the optical resonator rings in an optical transmitter or an optical receiver involves reassigning one or more of the optical resonator rings to different laser lines, wherein the reassignment is based on mitigating an impact on energy consumption from adding or removing heat from the optical resonator rings to bring their resonant wavelengths coincident with the laser lines.

Abstract: Random sequence generators utilizing one or more noise generators that include an inverter chain with at least one input stage inverter configured with resistive feedback and additional inverters configured in series with the at least one input stage inverter, wherein an output of the inverter chain is coupled to a bit sequence generator.

Abstract: Physically unclonable function cells based on bit-storing machine-memory circuits include a pair of parallel circuit branches, each of the parallel branches including a first transistor configured to be always-ON when the physically unclonable function cell is powered, and a second transistor cross-coupled to an opposite one of the parallel branches.

Abstract: A dense wave division multiplex (DWDM) receiver includes receiver lanes each configured to detect signals encoded in a different electromagnetic frequency band. The DWDM receiver applies a clock signal received on a variable one of the receiver lanes to lock a frequency of an injection locked oscillator (ILO) of a clock distribution network, and receiver lanes that are configured to receive data signals generate resonance on the clock distribution network. The resonant signal from the clock distribution network is applied to sample the received data signals.

Abstract: A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value.

Abstract: PUF cells utilizing a dual-interlocking scheme demonstrating improved noise immunity and stability across different V/T conditions and different uses over time in noisy environments. The PUF cell may be advantageously utilized in conjunction with error detection techniques that screen out unstable cells. A set of such PUF cells utilized to generate a device-specific bit pattern, for example a master key.

Abstract: A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value.

Abstract: PUF cells utilizing a dual-interlocking scheme demonstrating improved noise immunity and stability across different V/T conditions and different uses over time in noisy environments. The PUF cell may be advantageously utilized in conjunction with error detection techniques that screen out unstable cells. A set of such PUF cells utilized to generate a device-specific bit pattern, for example a master key.

Abstract: A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes digital logic that in turn includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value. The digital logic further includes a loop filter coupled between the glitch detector and the oscillator. The loop filter variably adjusts the oscillator based on a frequency of each of the multiple samples to control an output frequency of each of the multiple different phases of the oscillator.

Abstract: A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes digital logic that in turn includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value. The digital logic further includes a loop filter coupled between the glitch detector and the oscillator. The loop filter variably adjusts the oscillator based on a frequency of each of the multiple samples to control an output frequency of each of the multiple different phases of the oscillator.

Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable characterization circuits are coupled to inputs to the bit generating cells to affect the outputs of the bit generating cells. Based on the effect of the characterization circuit(s) on the outputs of the bit generating cells, a subset less than all of the bit generating cells is selected.

Abstract: Bit generating cells are subjected to processes that accelerate aging-related characteristics before they are configured for use in the field (enrolled). Aging improves the reliability of the cells by shifting device characteristic in a direction that improves the cell behavior with respect not only to aging but also environment variations. Outputs of the cells are read, and the cells are reconfigured with a bias to output an opposite value, and then aged for enrollment.

Abstract: Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.

Abstract: Microring resonators are devices that includes a set of waveguides that guide light, where at least one of the waveguides is a closed loop that operates to increase an intensity of the light over each round-trip. Microring resonators can be configured to operate as light filters and/or light modulators, and have application, for example, in the field of optical communication technology. Due to temperature sensitivity of microring resonators, however, a heating device is needed to maintain a microring resonator at a desired temperature. The present disclosure provides a microring resonator heating device that includes at least two coaxially arranged contacts providing radial current flow to heat the microring resonator.

Abstract: This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.

Abstract: Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.

Abstract: Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.

Abstract: Bit generating cells are subjected to processes that accelerate aging-related characteristics before they are configured for use in the field (enrolled). Aging improves the reliability of the cells by shifting device characteristic in a direction that improves the cell behavior with respect not only to aging but also environment variations. Outputs of the cells are read, and the cells are reconfigured with a bias to output an opposite value, and then aged for enrollment.

Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable characterization circuits are coupled to inputs to the bit generating cells to affect the outputs of the bit generating cells. Based on the effect of the characterization circuit(s) on the outputs of the bit generating cells, a subset less than all of the bit generating cells is selected.