Abstract: A method for compensating an offset in a receiver is provided. The method includes receiving first data from a first sampler and receiving second data from a second sampler. The method also include determining a first average value from the boundary of the first data over a selected period of time; and sending an offset signal to the first sampler based on the first average value. The method may also include determining a second average value from the boundary of the second data over a selected period of time; and sending an offset signal to the second sampler based on the second average value of the boundary data.

Abstract: A circuit may include an amplifying circuit and a t-coil inductor. The amplifying circuit may include an input node, an output node, an amplifier, and a feedback loop. The feedback loop may be coupled between the input node and the output node. The amplifying circuit may be configured to receive a current signal on the input node and to output a voltage signal based on the current signal on the output node. The t-coil inductor may include a first portion and a second portion. A first node of the first portion may be coupled to the input node of the amplifying circuit and the second portion may be included in the feedback loop.

Abstract: A system for signal generation may include a phase-locked-loop including a first oscillator. The system may also include a second oscillator. The first oscillator may be configured to generate a first signal based on a phase-locked-loop control signal generated by the phase-locked-loop. The second oscillator may be configured to generate a second signal based on the phase-locked-loop control signal such that a free-running frequency of the first signal is approximately equal to a free-running frequency of the second signal to obtain injection locking between the first oscillator and the second oscillator when energy from the first oscillator is coupled into the second oscillator.

Abstract: A multiplexer may include a first circuit, a second circuit, and a third circuit. The first circuit may be configured to receive a first input signal and a first trigger signal and to output a first output signal that may be based on the first input signal during a first level of the first trigger signal and may be at a known level during a second level of the first trigger signal. The second circuit may be configured to receive a second input signal and a second trigger signal and to output a second output signal that may be based on the second input signal during a first level of the second trigger signal and may be at the known level during a second level of the second trigger signal. The third circuit may be configured to output a third output signal based on the first and second output signals.

Abstract: In one embodiment, a receiver may receive a signal from a transmitter. The receiver may include a first sampler that may sample the signal when the value of the signal is zero. The receiver may further include a second sampler that may sample the signal halfway between a time when the first sampler samples the signal and the next time when the first sampler samples the signal to produce a set of sampled values. The receiver may be further operable to determine that a sampled value in the set of sampled values is a logic 1 if the sampled value is greater than the value of a reference voltage and that the sampled value is a logic 0 if the sampled value is less than the value of the reference voltage.

Abstract: A data signal delay system may include a delay unit and a phase interpolation unit. The delay unit may include multiple delay elements that each have an element delay. The delay unit may be configured to generate multiple delay signals by delaying a data signal using the delay elements such that each of the delay signals has a different delay. The phase interpolation unit may be coupled to the delay unit and may include a mixer. The mixer may be configured to mix two of the delay signals based on mixing weights selected for the two delay signals to generate a final delayed data signal that is the data signal delayed by a final delay. The mixing weights may be selected based on the final delay.

Abstract: An optical transmitter is disclosed. In accordance with some embodiments of the present disclosure, an optical transmitter may comprise a vertical-cavity surface-emitting laser (VCSEL) and a VCSEL driver. The VCSEL driver may comprise an input stage configured to receive a voltage signal and a low-impedance output stage comprising an input coupled to the input stage and a low-impedance output coupled to the VCSEL and configured to provide a modulated output current to the VCSEL.

Abstract: A method may include applying an input differential voltage to input terminals of an amplifier, a first input terminal coupled to a gate of a first transistor and a second input terminal coupled to a gate of a second transistor. The method may also include varying a gain of the amplifier by varying at least one of: a resistance of a first resistor, the first resistor coupled between a source of the first transistor and a source of the second transistor; and a resistance of a second resistor, the second resistor coupled between a source of a third transistor and a source of a fourth transistor; wherein: the third transistor is coupled at its drain to the drain of the first transistor; and the fourth transistor is coupled at its drain to the drain of the second transistor and a gate of the third transistor and coupled at its gate to the drain of the third transistor.

Abstract: In one embodiment, a method includes applying, by a transimpedance amplifier at a receiving end of a communication link, equalization to a signal carried by the communication link at the receiving end of the communication link.

Abstract: In one embodiment, a method includes adjusting a first frequency of a first clock signal based on a frequency difference between the first frequency and a reference clock signal frequency of a reference clock signal, and further adjusting the first frequency and a first phase of the first clock signal based on a phase difference between the first clock signal and an input data bit stream and the frequency difference between the first frequency and the reference clock signal frequency to substantially lock the first frequency and the first phase of the first clock signal to the input data bit frequency and input data bit phase of the input data bit stream.

Abstract: In one embodiment, a driver circuit of a vertical-cavity surface-emitting laser (VCSEL) includes bias current sources, modulation current sources, and a switch component connected to the bias current sources at a first node and to the modulation current sources at second nodes; the switch component is configured to modulate a current from the bias and modulation current sources based on an input signal to the switch component; and the switch component is also configured to provide the modulated current to the VCSEL through a folded cascode transistor.

Abstract: A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.

Abstract: A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.

Abstract: A method may include applying an input differential voltage to input terminals of an amplifier, a first input terminal coupled to a gate of a first transistor and a second input terminal coupled to a gate of a second transistor. The method may also include varying a gain of the amplifier by varying at least one of: a resistance of a first resistor, the first resistor coupled between a source of the first transistor and a source of the second transistor; and a resistance of a second resistor, the second resistor coupled between a source of a third transistor and a source of a fourth transistor; wherein: the third transistor is coupled at its drain to the drain of the first transistor; and the fourth transistor is coupled at its drain to the drain of the second transistor and a gate of the third transistor and coupled at its gate to the drain of the third transistor.

Abstract: A circuit may include a phase difference selector, a clock signal generator, a reference clock phase detector, and a data signal phase detector. The phase difference selector may be configured to select one of multiple reference clock phase difference signals generated by the reference clock phase detector based on a difference in phase between multiple clock signals and a reference clock. The clock signal generator may be configured to generate the multiple clock signals based on the selected reference clock phase difference signal. The data signal phase detector may be configured to generate a data phase difference signal based on differences in phase between the clock signals and a data signal. The data phase difference signal may be used by the phase difference selector to select one of the reference clock phase difference signals.

Abstract: In one embodiment, a circuit, which comprises a resistor and a pMOS or cMOS transistor, has the characteristic of an inductor and produces an inductive impedance that operates over a substantially full range of a direct-current bias.

Abstract: A current mode logic latch may include a first hold stage transistor coupled at its drain terminal to the drain terminal of a first sample stage transistor. A second hold stage transistor is coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. A first hold stage current source is coupled to a source terminal of the first hold stage transistor. A second hold stage current source is coupled to a source terminal of the second hold stage transistor. The hold stage switch is coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.

Abstract: In one embodiment, a driver circuit of a vertical-cavity surface-emitting laser (VCSEL) includes bias current sources, modulation current sources, and a switch component connected to the bias current sources at a first node and to the modulation current sources at second nodes; the switch component is configured to modulate a current from the bias and modulation current sources based on an input signal to the switch component; and the switch component is also configured to provide the modulated current to the VCSEL through a folded cascode transistor.

Abstract: In one embodiment, a method includes applying, by a transimpedance amplifier at a receiving end of a communication link, equalization to a signal carried by the communication link at the receiving end of the communication link.

Abstract: In one embodiment, a circuit includes a voltage-controlled oscillator (VCO) configured to generate k first clock signals that each have a first phase based on a charge-pump control voltage signal; one or more phase interpolators (PIs) configured to receive the k first clock signals and one or more first feedback controls signals and generate m second clock signals that each have a second phase based on the k first clock signals and the one or more first feedback control signals; a first phase detector (PD) configured to receive the m second clock signals and generate the one or more first feedback control signals based on the m second clock signals; a second PD configured to generate one or more second feedback control signals based on the m second clock signals; and a charge pump configured to output the charge-pump control voltage signal based on the second feedback control signals.