Abstract: According to some embodiments, the present disclosure may relate to a method of neural network analysis that includes receiving a first electronic message, storing it in a storage device, and decoding it to output a first data structure. The first electronic message may reference a first dictionary entry correlating the first electronic message to the first data structure including more bits than the first message. The method may also include providing the first data structure to a processing element to perform a data structure analysis on the first data structure yielding a second data structure including more bits than the first electronic message. The method may also include matching the second data structure to a second dictionary entry correlating the second data structure to a second electronic message that includes fewer bits than the second data structure, and transmitting the second electronic message instead of the second data structure.

Abstract: A method and system for implementing nonlinear transmitter equalization may employ a feed-forward equalizer that applies transition-dependent delays at each tap. Each delay element in a delay line may include independent controls for the delays to be applied to rising transitions and for the delays to be applied to falling transitions. Different delays may be applied to transitions between any two levels in a signal that is encoded using three or more analog levels. Different amounts of weighting may be applied to the output of each delay element in the delay line by respective tap weighing elements. A combiner circuit may generate an output for the equalizer as a linear combination of the weighted outputs of the delay elements. The output of the equalizer may be an input to a vertical cavity surface emitting laser (VCSEL) and may compensate for a nonlinearity of the VCSEL.

Abstract: A method and system for implementing phase-compensating equalization in an optical transmitter may employ a phase-compensating equalizer that includes an all-pass filter and a low-pass filter operating in parallel on an input signal to be transmitted in an optical communication network. The phase-compensating equalizer may include a circuit that combines the outputs of the two filters (e.g., through addition or subtraction) to generate an output of the equalizer. The output of the phase-compensating equalizer may be directed to a vertical cavity surface emitting laser (VCSEL) in the transmitter, and may compensate for at least a portion of the phase distortion resulting from the inherent phase characteristics of the VCSEL. The use of the phase-compensating equalizer may improve the phase response of an optical transmitter operating at data rates of tens of gigabits per second and beyond.

Abstract: A method includes applying a voltage to an optical ring resonator circuit to adjust a resonance condition of a ring waveguide included in the optical ring resonator circuit. The method also includes detecting an amount of current generated by the optical ring resonator circuit and determining the resonance condition of the ring waveguide based on the detected amount of current.

Abstract: A phase detection circuit includes a first sample circuit, a second sample circuit, and a third sample circuit. The first sample circuit may be configured to sample a first signal based on a first phase of a second signal to generate a first sample of the first signal and to output the first sample. The second sample circuit may be configured to sample the first signal based on a second phase of the second signal to generate a second sample of the first signal and to output second sample. The third sample circuit coupled to the first sample circuit and to the second sample circuit. The third sample circuit may be configured to sample the first sample based on a change of the second sample to generate a third sample and to output the third sample.

Abstract: A circuit may include an amplifying circuit and a t-coil inductor. The amplifying circuit may include an input node, an output node, an amplifier, and a feedback loop. The feedback loop may be coupled between the input node and the output node. The amplifying circuit may be configured to receive a current signal on the input node and to output a voltage signal based on the current signal on the output node. The t-coil inductor may include a first portion and a second portion. A first node of the first portion may be coupled to the input node of the amplifying circuit and the second portion may be included in the feedback loop.

Abstract: A circuit may include an input node, a first intermediate node, a second intermediate node and an output node. The circuit may also include a first gain stage electrically coupled between the input node and the first intermediate node. Additionally, the circuit may include a second gain stage electrically coupled between the first intermediate node and the second intermediate node. Further, the circuit may include a third gain stage electrically coupled between the second intermediate node and the output node. The circuit may also include a first feedback that includes a first feedback element electrically coupled between the first intermediate node and the second intermediate node. In addition, the circuit may include a second feedback that includes a second feedback element electrically coupled between the output node and the first intermediate node.

Abstract: A charge pump circuit may include an output node, a current source circuit, a current sink circuit, a first amplifier circuit, and a second amplifier circuit. The current source circuit may be configured to source current to the output node. The current sink circuit may be configured to sink current from the output node. The first amplifier circuit may be configured to adjust a first amount of current sourced by the current source circuit based on a voltage on the output node. The second amplifier circuit may be configured to adjust the first amount of current sourced by the current source circuit or a second amount of current sunk by the current sink circuit based on the voltage on the output node.

Abstract: A method includes applying a voltage to an optical ring resonator circuit to adjust a resonance condition of a ring waveguide included in the optical ring resonator circuit. The method also includes detecting an amount of current generated by the optical ring resonator circuit and determining the resonance condition of the ring waveguide based on the detected amount of current.

Abstract: An electronic device includes a transmission module communicatively coupled to a synchronizer. The transmission module is configured to transform received data for transmission, receive a first instruction from the synchronizer, based on the instruction adjust the phase of a clock signal used to time the transformation of the received data, and send the adjusted clock signal to the synchronizer. The synchronizer is configured to receive the adjusted clock signal, receive a data signal comprising a frequency and a phase of data to be transmitted, based on the adjusted clock signal and the data signal, determine a second instruction for the transmission module, and provide the second instruction to the transmission module.

Abstract: A clock multiplication and distribution system includes a first phase-lock-loop circuit, a second phase-lock-loop circuit, and a clock distribution network that electrically couples the first phase-lock-loop circuit and the second phase-lock-loop circuit. The first phase-lock-loop circuit may include a first feedback loop that includes a first integer divider circuit and may be configured to generate a first clock using a reference clock. A frequency of the first clock may be greater than a frequency of the reference clock. The second phase-lock-loop circuit may include a second feedback loop that includes a second integer divider circuit and may be configured to generate a second clock using the first clock. A frequency of the second clock may be greater than the frequency of the first clock.

Abstract: A circuit may include a pulse generation circuit configured to receive a first clock signal with a first-clock rate and a first-clock duty cycle. The pulse generation circuit may be configured to generate, based on the first clock signal, a pulse signal with a pulse frequency and with a pulse duty cycle that is smaller than the first-clock duty cycle. The circuit may also include a sub-harmonic injection locking oscillator configured to receive the pulse signal. The sub-harmonic injection locking oscillator may be configured to output, based on the pulse signal, a second clock signal with a second-clock rate that is greater than the first-clock rate and greater than the pulse frequency.

Abstract: A circuit may include a pulse generation circuit configured to receive a first clock signal with a first-clock rate and a first-clock duty cycle. The pulse generation circuit may be configured to generate, based on the first clock signal, a pulse signal with a pulse frequency and with a pulse duty cycle that is smaller than the first-clock duty cycle. The circuit may also include a sub-harmonic injection locking oscillator configured to receive the pulse signal. The sub-harmonic injection locking oscillator may be configured to output, based on the pulse signal, a second clock signal with a second-clock rate that is greater than the first-clock rate and greater than the pulse frequency.

Abstract: A system for signal generation may include a phase-locked-loop including a first oscillator. The system may also include a second oscillator. The first oscillator may be configured to generate a first signal based on a phase-locked-loop control signal generated by the phase-locked-loop. The second oscillator may be configured to generate a second signal based on the phase-locked-loop control signal such that a free-running frequency of the first signal is approximately equal to a free-running frequency of the second signal to obtain injection locking between the first oscillator and the second oscillator when energy from the first oscillator is coupled into the second oscillator.

Abstract: A method may include applying an input differential voltage to input terminals of an amplifier, a first input terminal coupled to a gate of a first transistor and a second input terminal coupled to a gate of a second transistor. The method may also include varying a gain of the amplifier by varying at least one of: a resistance of a first resistor, the first resistor coupled between a source of the first transistor and a source of the second transistor; and a resistance of a second resistor, the second resistor coupled between a source of a third transistor and a source of a fourth transistor; wherein: the third transistor is coupled at its drain to the drain of the first transistor; and the fourth transistor is coupled at its drain to the drain of the second transistor and a gate of the third transistor and coupled at its gate to the drain of the third transistor.

Abstract: A method for compensating an offset in a receiver is provided. The method includes receiving first data from a first sampler and receiving second data from a second sampler. The method also include determining a first average value from the boundary of the first data over a selected period of time; and sending an offset signal to the first sampler based on the first average value. The method may also include determining a second average value from the boundary of the second data over a selected period of time; and sending an offset signal to the second sampler based on the second average value of the boundary data.

Abstract: A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.

Abstract: A clock multiplication and distribution system includes a first phase-lock-loop circuit, a second phase-lock-loop circuit, and a clock distribution network that electrically couples the first phase-lock-loop circuit and the second phase-lock-loop circuit. The first phase-lock-loop circuit may include a first feedback loop that includes a first integer divider circuit and may be configured to generate a first clock using a reference clock. A frequency of the first clock may be greater than a frequency of the reference clock. The second phase-lock-loop circuit may include a second feedback loop that includes a second integer divider circuit and may be configured to generate a second clock using the first clock. A frequency of the second clock may be greater than the frequency of the first clock.

Abstract: An optical transmitter is disclosed. In accordance with some embodiments of the present disclosure, an optical transmitter may comprise a vertical-cavity surface-emitting laser (VCSEL) and a VCSEL driver. The VCSEL driver may comprise an input stage configured to receive a voltage signal and a low-impedance output stage comprising an input coupled to the input stage and a low-impedance output coupled to the VCSEL and configured to provide a modulated output current to the VCSEL.

Abstract: A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.