Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data receiver front ends.

Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty cycle error, combined with a local offset value for each data lane, and is applied to data receiver front ends.

Abstract: A linear regulator for applications with low area constraint resulting in limited load decoupling capacitance that introduces a compensating zero in the regulator loop to counteract the loss of phase margin and further introduces a feed-forward noise cancellation path operating over a wide frequency range covering a first package resonance frequency. The feed-forward path has low power consumption and improves the power-supply rejection ratio.

Abstract: According to some embodiments, the present disclosure may relate to a method of neural network analysis that includes receiving a first electronic message, storing it in a storage device, and decoding it to output a first data structure. The first electronic message may reference a first dictionary entry correlating the first electronic message to the first data structure including more bits than the first message. The method may also include providing the first data structure to a processing element to perform a data structure analysis on the first data structure yielding a second data structure including more bits than the first electronic message. The method may also include matching the second data structure to a second dictionary entry correlating the second data structure to a second electronic message that includes fewer bits than the second data structure, and transmitting the second electronic message instead of the second data structure.

Abstract: A linear regulator for applications with low area constraint resulting in limited load decoupling capacitance that introduces a compensating zero in the regulator loop to counteract the loss of phase margin and further introduces a feed-forward noise cancellation path operating over a wide frequency range covering a first package resonance frequency. The feed-forward path has low power consumption and improves the power-supply rejection ratio.

Abstract: A DC-DC converter circuit includes a switched tank converter configured to output a switching waveform. The DC-DC converter circuit further includes a transformer coupled to the switched tank converter to receive the switching waveform output by the switched tank converter across a primary winding of the transformer.

Abstract: A signal transceiver includes a signal transmitter driving a first differential link between a supply voltage of the signal transmitter and a fraction of the supply voltage, and driving a second differential link between the faction of the supply voltage and a reference ground. The signal transceiver also includes a signal receiver in which the first differential link is coupled to a gate node of an NMOS transistor and to a source node of a PMOS transistor; and the second differential link is coupled to a source node of the NMOS transistor and to a gate node of the PMOS transistor.

Abstract: A method of generating mapping dictionaries for neural networks may be provided. A method may include receiving, at a current layer, encoded activation addresses from a previous layer and encoded weight addresses. The method may also include decoding the encoded activation addresses to generate decoded activation addresses, and decoding the encoded weight addresses to generate decoded weight addresses. Further, the method may include generating original activation addresses from the decoded activation addresses and the decoded weight addresses. Moreover, the method may include matching the original activation addresses to a mapping dictionary to generate encoded activation addresses for the current layer.

Abstract: A single-ended signal transmission system recovers a noise signal associated with a data input signal and uses the recovered noise signal to compensate for noise on the data input signal. The noise signal may be recovered from a noise reference signal line, or clock signal line, or a data signal line associated with a DC-balanced data input signal. The recovered noise signal may be represented as an analog signal or a digital signal. The recovered noise signal may be processed to compensate for DC offset and nonlinearities associated with one or more different input buffers. In one embodiment, the recovered noise signal includes frequency content substantially below a fundamental frequency for data transmission through the data input signal.

Abstract: A method of updating a neural network may be provided. A method may include computing gradients for an operating matrix of a current layer of the neural network based on data of at least one of the current layer and at least one other layer of the neural network. The method may also include updating the operating matrix based on the computed gradients. Further, the method may include updating an indexing matrix of the current layer based on the updated operating matrix.

Abstract: A single-ended signal transmission system recovers a noise signal associated with a data input signal and uses the recovered noise signal to compensate for noise on the data input signal. The noise signal may be recovered from a noise reference signal line, or clock signal line, or a data signal line associated with a DC-balanced data input signal. The recovered noise signal may be represented as an analog signal or a digital signal. The recovered noise signal may be processed to compensate for DC offset and nonlinearities associated with one or more different input buffers. In one embodiment, the recovered noise signal includes frequency content substantially below a fundamental frequency for data transmission through the data input signal.

Abstract: A single-ended signal transmission system recovers a noise signal associated with a data input signal and uses the recovered noise signal to compensate for noise on the data input signal. The noise signal may be recovered from a noise reference signal line, or clock signal line, or a data signal line associated with a DC-balanced data input signal. The recovered noise signal may be represented as an analog signal or a digital signal. The recovered noise signal may be processed to compensate for DC offset and nonlinearities associated with one or more different input buffers. In one embodiment, the recovered noise signal includes frequency content substantially below a fundamental frequency for data transmission through the data input signal.

Abstract: A multi-stage amplifier circuit equalizes an input signal through multiple signal amplification paths. DC gain is kept substantially constant over frequency, while adjustable high-frequency gain provides equalization (e.g., peaking). Various embodiments include a common source topology, a common gate topology, differential signaling topologies, and a topology suitable for stabilizing a voltage supply against high-frequency transient loads. A system may include one or more integrated circuits that may each include one or more instances of the multi-stage amplifier.

Abstract: A single-ended signal transmission system recovers a noise signal associated with a data input signal and uses the recovered noise signal to compensate for noise on the data input signal. The noise signal may be recovered from a noise reference signal line, or clock signal line, or a data signal line associated with a DC-balanced data input signal. The recovered noise signal may be represented as an analog signal or a digital signal. The recovered noise signal may be processed to compensate for DC offset and nonlinearities associated with one or more different input buffers. In one embodiment, the recovered noise signal includes frequency content substantially below a fundamental frequency for data transmission through the data input signal.

Abstract: A method may include hardwiring: a first dynamic input of M slices in a section of a sliced architecture to receive a main data sample; and a second dynamic input of each of X and Y slices to respectively receive a first or second delayed data sample, X, Y being subsets of M. A slice current may be multiplied with: the data sample in each of A of the M slices; and the first delayed data sample in each of B of the X slices. The method may also include summing: outputs of the A slices to obtain a weighted output current of the data sample; outputs of the B slices to obtain a weighted output current of the first delayed data sample; and the weighted output currents of the main data sample and of the first delayed data sample to obtain a net weighted output current of the section.

Abstract: A method of updating a neural network may be provided. A method may include computing gradients for an operating matrix of a current layer of the neural network based on data of at least one of the current layer and at least other layer of the neural network. The method may also include updating the operating matrix based on the computed gradients. Further, the method may include updating an indexing matrix of the current layer based on the updated operating matrix.

Abstract: A method of measuring linearity characteristics of a delay line may be provided. The method may include generating an output signal from a receiver including a delay line. The method may also include measuring linearity characteristics of the delay line based on a target performance parameter of the output signal.

Abstract: A phase detection circuit includes a first sample circuit, a second sample circuit, and a third sample circuit. The first sample circuit may be configured to sample a first signal based on a first phase of a second signal to generate a first sample of the first signal and to output the first sample. The second sample circuit may be configured to sample the first signal based on a second phase of the second signal to generate a second sample of the first signal and to output second sample. The third sample circuit coupled to the first sample circuit and to the second sample circuit. The third sample circuit may be configured to sample the first sample based on a change of the second sample to generate a third sample and to output the third sample.

Abstract: A method of generating mapping dictionaries for neural networks may be provided. A method may include receiving, at a current layer, encoded activation addresses from a previous layer and encoded weight addresses. The method may also include decoding the encoded activation addresses to generate decoded activation addresses, and decoding the encoded weight addresses to generate decoded weight addresses. Further, the method may include generating original activation addresses from the decoded activation addresses and the decoded weight addresses. Moreover, the method may include matching the original activation addresses to a mapping dictionary to generate encoded activation addresses for the current layer.

Abstract: A charge pump circuit may include an output node, a current source circuit, a current sink circuit, a first amplifier circuit, and a second amplifier circuit. The current source circuit may be configured to source current to the output node. The current sink circuit may be configured to sink current from the output node. The first amplifier circuit may be configured to adjust a first amount of current sourced by the current source circuit based on a voltage on the output node. The second amplifier circuit may be configured to adjust the first amount of current sourced by the current source circuit or a second amount of current sunk by the current sink circuit based on the voltage on the output node.