Abstract: In one embodiment, a phase interpolator with a phase range of n degrees, where 0<n?360, and having m reference signals, where m?2, and a control signal as input, and producing an output signal with a phase within the phase range using one or more of the m reference signals based on a control code provided by the control signal. The phase interpolator comprises one or more circuits configured to: divide the phase range of n degrees into k sections, wherein k>m; and for each of the k sections, select a relative gain of one or more weights assigned to the one or more reference signals, respectively, with respect to the control code provided by the control signal.

Abstract: A circuit that includes an amplifier circuit with an input impedance due to an input resistance and an input capacitance of the amplifier circuit. The input impedance of the amplifier circuit may vary with frequency. The amplifier circuit may include an amplifier and a feedback circuit configured to provide feedback to the amplifier and to maintain the input impedance at a specified value at a selected frequency by increasing the input resistance of the amplifier circuit at the selected frequency.

Abstract: In one embodiment, one or more circuits convert an n-bit control code of a phase interpolator to a coupling control signal of k-bit wide. The one or more circuits couple one or more output signals of the phase interpolator to a reference clock of the phase interpolator based on the coupling control signal.

Abstract: A circuit may include a phase difference selector, a clock signal generator, a reference clock phase detector, and a data signal phase detector. The phase difference selector may be configured to select one of multiple reference clock phase difference signals generated by the reference clock phase detector based on a difference in phase between multiple clock signals and a reference clock. The clock signal generator may be configured to generate the multiple clock signals based on the selected reference clock phase difference signal. The data signal phase detector may be configured to generate a data phase difference signal based on differences in phase between the clock signals and a data signal. The data phase difference signal may be used by the phase difference selector to select one of the reference clock phase difference signals.

Abstract: A tunable clock distribution system that includes a clock network including an inductive circuit and a capacitive circuit where at least one of the capacitive circuit or the inductive circuit is tunable. The tunable clock distribution system may further include a driving circuit and a phase determiner. The driving circuit may be configured to receive a clock signal and to distribute a resonant clock signal based on the clock signal to the clock network. The phase determiner may be configured to receive the clock signal and the resonant clock signal and to determine whether the clock signal and the resonant clock signal have a predetermined phase difference. When the clock signal and the resonant clock signal do not have the predetermined phase difference, the phase determiner may be configured to tune at least one of the capacitive circuit or the inductive circuit.

Abstract: A current mode logic latch may include a first hold stage transistor coupled at its drain terminal to the drain terminal of a first sample stage transistor. A second hold stage transistor is coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. A first hold stage current source is coupled to a source terminal of the first hold stage transistor. A second hold stage current source is coupled to a source terminal of the second hold stage transistor. The hold stage switch is coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.

Abstract: A method may include applying an input differential voltage to input terminals of an amplifier, a first input terminal coupled to a gate of a first transistor and a second input terminal coupled to a gate of a second transistor. The method may also include varying a gain of the amplifier by varying at least one of: a resistance of a first resistor, the first resistor coupled between a source of the first transistor and a source of the second transistor; and a resistance of a second resistor, the second resistor coupled between a source of a third transistor and a source of a fourth transistor; wherein: the third transistor is coupled at its drain to the drain of the first transistor; and the fourth transistor is coupled at its drain to the drain of the second transistor and a gate of the third transistor and coupled at its gate to the drain of the third transistor.

Abstract: A circuit that includes an amplifier circuit with an input impedance due to an input resistance and an input capacitance of the amplifier circuit. The input impedance of the amplifier circuit may vary with frequency. The amplifier circuit may include an amplifier and a feedback circuit configured to provide feedback to the amplifier and to maintain the input impedance at a specified value at a selected frequency by increasing the input resistance of the amplifier circuit at the selected frequency.

Abstract: In one embodiment, one or more circuits convert an n-bit control code of a phase interpolator to a coupling control signal of k-bit wide. The one or more circuits couple one or more output signals of the phase interpolator to a reference clock of the phase interpolator based on the coupling control signal.

Abstract: An electronic device includes a transmission module communicatively coupled to a synchronizer. The transmission module is configured to transform received data for transmission, receive a first instruction from the synchronizer, based on the instruction adjust the phase of a clock signal used to time the transformation of the received data, and send the adjusted clock signal to the synchronizer. The synchronizer is configured to receive the adjusted clock signal, receive a data signal comprising a frequency and a phase of data to be transmitted, based on the adjusted clock signal and the data signal, determine a second instruction for the transmission module, and provide the second instruction to the transmission module.

Abstract: In one embodiment, a method includes receiving input data bits over data channels; receiving deskew channel bits constituting frames that each comprise ones of the input data bits; determining frame boundaries; mapping each of the input data bits in each of the frames to one of the data channels; for each set of the frames, comparing the input data bits in the set with the input data bits in the corresponding input data words; determining relative delays among the data channels and the deskew channel; when non-zero delays are determined, rearranging the input data bits to reduce the delays; and when it is determined that one or more of the data channels have a delay of greater than a predetermined number of data-channel clock periods relative to a particular data channel, delaying input data bits in the particular data channel by an additional number of input data bits.

Abstract: In one embodiment, a phase interpolator with a phase range of n degrees, where 0<n?360, and having m reference signals, where m?2, and a control signal as input, and producing an output signal with a phase within the phase range using one or more of the m reference signals based on a control code provided by the control signal. The phase interpolator comprises one or more circuits configured to: divide the phase range of n degrees into k sections, wherein k>m; and for each of the k sections, select a relative gain of one or more weights assigned to the one or more reference signals, respectively, with respect to the control code provided by the control signal.

Abstract: In one embodiment, a method includes adjusting a first frequency of a first clock signal based on a frequency difference between the first frequency and a reference clock signal frequency of a reference clock signal, and further adjusting the first frequency and a first phase of the first clock signal based on a phase difference between the first clock signal and an input data bit stream and the frequency difference between the first frequency and the reference clock signal frequency to substantially lock the first frequency and the first phase of the first clock signal to the input data bit frequency and input data bit phase of the input data bit stream.

Abstract: In one embodiment, a circuit, which comprises a resistor and a pMOS or cMOS transistor, has the characteristic of an inductor and produces an inductive impedance that operates over a substantially full range of a direct-current bias.

Abstract: In one embodiment, a transmitter can bias a vertical-cavity surface-emitting laser (VCSEL) coupled to an optical medium. The biasing of the VCSEL determines at least in part an optical power output by the VCSEL to the optical medium. The transmitter can also modulate the VCSEL with data to transmit the data optically through the optical medium to a receiver; receive from the receiver through a feedback channel an error vector representing a degradation in performance of the VCSEL sensed by the receiver or an instruction vector comprising one or more coefficients for use in biasing the VCSEL; and adjust the biasing of the VCSEL based on the error vector or the instruction vector to regulate the optical power output by the VCSEL to the optical medium.

Abstract: In one embodiment, a receiver may receive a signal from a transmitter. The receiver may include a first sampler that may sample the signal when the value of the signal is zero. The receiver may further include a second sampler that may sample the signal halfway between a time when the first sampler samples the signal and the next time when the first sampler samples the signal to produce a set of sampled values. The receiver may be further operable to determine that a sampled value in the set of sampled values is a logic 1 if the sampled value is greater than the value of a reference voltage and that the sampled value is a logic 0 if the sampled value is less than the value of the reference voltage.

Abstract: In one embodiment, a transmitter can bias a vertical-cavity surface-emitting laser (VCSEL) coupled to an optical medium. The biasing of the VCSEL determines at least in part an optical power output by the VCSEL to the optical medium. The transmitter can also modulate the VCSEL with data to transmit the data optically through the optical medium to a receiver; receive from the receiver through a feedback channel an error vector representing a degradation in performance of the VCSEL sensed by the receiver or an instruction vector comprising one or more coefficients for use in biasing the VCSEL; and adjust the biasing of the VCSEL based on the error vector or the instruction vector to regulate the optical power output by the VCSEL to the optical medium.

Abstract: In one embodiment, a method includes receiving a first input stream, generating a first clock, sampling the first input stream based on the first clock, detecting a first phase difference between the first input stream and the first clock to generate a clock-correction signal and a first select signal, and generating a first recovered stream based on the first select signal. The method may additionally include receiving a second input stream, generating a second clock, sampling the second input stream based on the second clock, detecting a second phase difference between the second input stream and the second clock to generate a clock-correction signal and a second select signal, and generating a second recovered stream based on the second select signal. The method may further include adjusting the clocks based on the first and second clock-correction signals and combining the first and second recovered data streams to generate an output.

Abstract: In one embodiment, a method includes receiving first and second input streams comprising first and second input data bits, respectively. The method includes generating first and second recovered clocks based on the first and second input streams, respectively. The method includes retiming and demultiplexing the first and second input data bits to generate n first recovered streams and n second recovered streams, respectively, each comprising first and second recovered data bits, respectively. The method further includes determining a phase difference between the first and second recovered clocks; aligning the first recovered data bits with the second recovered data bits based at least in part on a value of n and the phase difference; combining the first and second recovered data bits to generate an output stream; and retiming the first and second recovered data bits in the output stream based on either the first or second recovered clock.

Abstract: In one embodiment, a method includes accessing a reference clock having a reference clock frequency and reference clock phase; generating an output clock having an output clock phase and output clock frequency that is a function of an analog control voltage setting and a frequency gain curve; fixing the analog control voltage setting to a predetermined voltage; selecting one of the frequency gain curves within a predetermined frequency range of the reference clock frequency at the analog control voltage setting; adjusting the analog control voltage setting to adjust the output clock frequency to be within another predetermined frequency range of the reference clock frequency; and adjusting the output clock phase to be within a predetermined phase range of an input data phase of the input data stream.