Patents by Inventor Nikola Nedovic

Nikola Nedovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7688122
    Abstract: In particular embodiments, a charge pump includes a first input transistor operable to receive an up signal and in response to receiving the UP signal, transmit a corresponding output current from a positive power supply to an output node. The charge pump further includes a second input transistor operable to receive a down signal and in response to receiving the DN signal, transmit a second corresponding output current from a negative power supply to the output node. Additionally, the charge pump includes a first cascode transistor and a second cascode transistor positioned in a first current path between the first input transistor and the output node, and a third cascode transistor and a fourth cascode transistor positioned in a second current path between the second input transistor and the output node. The charge pump further includes a current mirror coupled to gates of the first, second, third, and fourth cascode transistors.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: March 30, 2010
    Assignee: Fujitsu Limited
    Inventor: Nikola Nedovic
  • Patent number: 7629817
    Abstract: In particular embodiments, an apparatus includes a first transistor connected at the gate to a first input signal voltage and a second transistor connected at the gate to a second input signal voltage. The apparatus further includes a deactivation element coupled to the transistors, the deactivation element being operable to deactivate the first and second transistors by selectively transmitting a deactivation current to a first terminal of the first transistor and a second terminal of the second transistor thereby raising a voltage on the first and second terminals to a value large enough to deactivate the first and second transistors. In particular embodiments, activating the first or second transistor transmits a signal from the apparatus and deactivating the first and second transistors prevents the signal from being transmitted from the apparatus.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: December 8, 2009
    Assignee: Fujitsu Limited
    Inventors: Nikola Nedovic, William W. Walker
  • Publication number: 20080191770
    Abstract: In particular embodiments, an apparatus includes a first transistor connected at the gate to a first input signal voltage and a second transistor connected at the gate to a second input signal voltage. The apparatus further includes a deactivation element coupled to the transistors, the deactivation element being operable to deactivate the first and second transistors by selectively transmitting a deactivation current to a first terminal of the first transistor and a second terminal of the second transistor thereby raising a voltage on the first and second terminals to a value large enough to deactivate the first and second transistors. In particular embodiments, activating the first or second transistor transmits a signal from the apparatus and deactivating the first and second transistors prevents the signal from being transmitted from the apparatus.
    Type: Application
    Filed: December 19, 2007
    Publication date: August 14, 2008
    Applicant: Fujitsu Limited
    Inventors: Nikola Nedovic, William W. Walker
  • Publication number: 20080191787
    Abstract: In particular embodiments, a charge pump includes a first input transistor operable to receive an up signal and in response to receiving the UP signal, transmit a corresponding output current from a positive power supply to an output node. The charge pump further includes a second input transistor operable to receive a down signal and in response to receiving the DN signal, transmit a second corresponding output current from a negative power supply to the output node. Additionally, the charge pump includes a first cascode transistor and a second cascode transistor positioned in a first current path between the first input transistor and the output node, and a third cascode transistor and a fourth cascode transistor positioned in a second current path between the second input transistor and the output node. The charge pump further includes a current mirror coupled to gates of the first, second, third, and fourth cascode transistors.
    Type: Application
    Filed: January 7, 2008
    Publication date: August 14, 2008
    Applicant: Fujitsu Limited
    Inventor: Nikola Nedovic
  • Publication number: 20080192873
    Abstract: In one embodiment, a method includes receiving a data signal comprising a plurality of bits. The method further includes generating a clock signal. A plurality of samples is acquired from the data signal at a sampling rate determined by the clock signal and it is determined whether a transition point from a first bit in the plurality of bits to a second bit in the plurality of bits occurs within the plurality of samples. If it is determined that the transition point occurs within the plurality of samples, a state machine comprising a plurality of states transitions from a first state to a second state. If the second state indicates a non-zero amount of phase displacement between the clock signal and the data signal, the clock signal is adjusted to correlate with the data signal.
    Type: Application
    Filed: January 30, 2008
    Publication date: August 14, 2008
    Applicant: Fujitsu Limited
    Inventors: Hirotaka Tamura, Nikola Nedovic, William W. Walker
  • Patent number: 7027345
    Abstract: Techniques, including a system and method, are disclosed for conditionally pre-charging a memory circuit, for example a flip-flop, and thus reducing power consumption. In an embodiment a method for reducing power consumption in a memory circuit, including, a pre-charged stage coupled to an evaluation stage by at least an internal node, is provided. The method includes setting an input of the pre-charged stage to a first high logic level. Next, responsive to the setting of the input, the internal node is set to a low logic level within a first transparency window. Then responsive to the setting of the internal node, the evaluation stage changes the output of the evaluation stage to a second high logic level within the first transparency window. Lastly, when the input remains at the first high-logic level, the internal node is maintained at the low logic level through at least a second transparency window.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: April 11, 2006
    Assignee: Fujitsu Limited
    Inventors: Nikola Nedovic, Vojin G. Oklobd{hacek over (z)}ija, William W. Walker
  • Patent number: 6693459
    Abstract: The present invention provides techniques, including a system and method, for improving speed in a flip-flop, having a pre-charged stage coupled to an evaluation stage. In one exemplary embodiment delay is reduced by using a conditional rather than an unconditional keeper, where the conditional keeper has the function of a keeper only under certain conditions. In some embodiments there is a conditional keeper in either the pre-charged stage or the evaluation stage or both stages. Another embodiment provides for the combining of the evaluation stage with one or more external logic functions.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: February 17, 2004
    Assignee: Fujitsu Limited
    Inventors: Nikola Nedovic, Vojin G. Oklobd{haeck over (z)}ija, William W. Walker
  • Patent number: 6646487
    Abstract: The invention relates generally to the field of electronic circuit design, and in particular to techniques for reducing hazards in a digital logic circuit, for example, a digital logic flip-flop circuit. In an embodiment of the present invention a method for reducing hazards in a flip-flop, including, a pre-charged stage coupled to an evaluation stage by at least an internal node, is provided. First, the pre-charged stage sets the internal node based on a data input. The evaluation stage is prevented from evaluating the internal node for a predetermined time period. After the predetermined time period, the internal node is evaluated by the evaluation stage to determine an output of the flip-flop.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: November 11, 2003
    Assignee: Fujitsu Limited
    Inventors: Nikola Nedovic, Vojin G. Oklobd{haeck over (z)}ija, William W. Walker
  • Publication number: 20030062925
    Abstract: The present invention provides techniques, including a system and method, for improving speed in a flip-flop, having a pre-charged stage coupled to an evaluation stage. In one exemplary embodiment delay is reduced by using a conditional rather than an unconditional keeper, where the conditional keeper has the function of a keeper only under certain conditions. In some embodiments there is a conditional keeper in either the pre-charged stage or the evaluation stage or both stages. Another embodiment provides for the combining of the evaluation stage with one or more external logic functions.
    Type: Application
    Filed: January 11, 2002
    Publication date: April 3, 2003
    Applicant: Fujitsu Limited
    Inventors: Nikola Nedovic, Vojin G. Oklobdzija, William W. Walker
  • Publication number: 20030062940
    Abstract: The invention relates generally to the field of electronic circuit design, and in particular to techniques for reducing hazards in a digital logic circuit, for example, a digital logic flip-flop circuit. In an embodiment of the present invention a method for reducing hazards in a flip-flop, including, a pre-charged stage coupled to an evaluation stage by at least an internal node, is provided. First, the pre-charged stage sets the internal node based on a data input. The evaluation stage is prevented from evaluating the internal node for a predetermined time period. After the predetermined time period, the internal node is evaluated by the evaluation stage to determine an output of the flip-flop.
    Type: Application
    Filed: January 11, 2002
    Publication date: April 3, 2003
    Applicant: Fujitsu Limited
    Inventors: Nikola Nedovic, Vojin G. Oklobdzija, William W. Walker
  • Publication number: 20030056129
    Abstract: Techniques, including a system and method, are disclosed for conditionally pre-charging a memory circuit, for example a flip-flop, and thus reducing power consumption. In an embodiment a method for reducing power consumption in a memory circuit, including, a pre-charged stage coupled to an evaluation stage by at least an internal node, is provided. The method includes setting an input of the pre-charged stage to a first high logic level. Next, responsive to the setting of the input, the internal node is set to a low logic level within a first transparency window. Then responsive to the setting of the internal node, the evaluation stage changes the output of the evaluation stage to a second high logic level within the first transparency window. Lastly, when the input remains at the first high-logic level, the internal node is maintained at the low logic level through at least a second transparency window.
    Type: Application
    Filed: January 11, 2002
    Publication date: March 20, 2003
    Applicant: Fujitsu Limited
    Inventors: Nikola Nedovic, Vojin G. Oklobdzija, William W. Walker