Patents by Inventor Nitin Deshpande

Nitin Deshpande has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9397071
    Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: July 19, 2016
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, John S. Guzek, Johanna M. Swan, Christopher J. Nelson, Nitin A. Deshpande, William J. Lambert, Charles A. Gealer, Feras Eid, Islam A. Salama, Kemal Aygun, Sasha N. Oster, Tyler N. Osborn
  • Publication number: 20160181218
    Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 23, 2016
    Inventors: Omkar G. Karhade, Nitin A. Deshpande, Debendra Mallik, Bassam M. Ziadeh, Yoshihiro Tomita
  • Publication number: 20160172323
    Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 16, 2016
    Applicant: Intel Corporation
    Inventors: YOSHIHIRO TOMITA, JIRO KUBOTA, OMKAR G. KARHADE, SHAWNA M. LIFF, KINYA ICHIKAWA, NITIN A. DESHPANDE
  • Publication number: 20160155705
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: January 22, 2016
    Publication date: June 2, 2016
    Inventors: Ravindranath V. Mahajan, Christopher J. Nelson, Omkar G. Karhade, Feras Eid, Nitin A. Deshpande, Shawna M. Liff
  • Publication number: 20160095220
    Abstract: Some example forms relate to an electronic package. The electronic package includes an electronic component and a substrate that includes a front side and a back side. The electronic component is mounted on the front side of the substrate and conductors are mounted on the back side of the substrate. The substrate is warped due to differences in the coefficients of thermal expansion between the electronic component and the substrate. An adhesive is positioned between the conductors on the back side of the substrate and an adhesive film is attached to the adhesive positioned between the conductors on the back side of the substrate.
    Type: Application
    Filed: September 25, 2014
    Publication date: March 31, 2016
    Inventors: Omkar Karhade, Nitin Deshpande, Nachiket Raravikar
  • Patent number: 9275955
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: March 1, 2016
    Assignee: INTEL CORPORATION
    Inventors: Ravindranath V. Mahajan, Christopher J. Nelson, Omkar G. Karhade, Feras Eid, Nitin A. Deshpande, Shawna M. Liff
  • Patent number: 9180541
    Abstract: A solder-flux composition is sprayed onto a substrate by rotating the solder-flux composition inside a spray cap, and before the solder-flux liquid exits the spray cap, perturbing the flow thereof with a fluid.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: November 10, 2015
    Assignee: INTEL CORPORATION
    Inventors: Harikrishnan Ramanan, Nitin Deshpande, Sabina J. Houle
  • Publication number: 20150318258
    Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.
    Type: Application
    Filed: July 10, 2015
    Publication date: November 5, 2015
    Applicant: INTEL CORPORATION
    Inventors: SANDEEP B. SANE, Shankar Ganapathysubramanian, Jorge Sanchez, Leonel R. Arana, Eric J. Li, Nitin A. Deshpande, Jiraporn Seangatith, Poh Chieh Benny Poon
  • Publication number: 20150318255
    Abstract: Ultrathin microelectronic die packages and methods of fabricating the same comprising attaching a microelectronic die to a substrate with a plurality of interconnects, and depositing an underfill material between the microelectronic die and the microelectronic substrate, and around the interconnects. An etchant may be introduced to a back surface of the microelectronic die to remove a portion thereof which reduces the thickness of the microelectronic die to form an ultrathin microelectronic die. In another embodiment, the etching of the microelectronic die forms an ultrathin microelectronic die having a curved surface between the ultrathin microelectronic die back surface and a sidewall thereof.
    Type: Application
    Filed: April 30, 2014
    Publication date: November 5, 2015
    Inventors: OMKAR G. KARHADE, NITIN A. DESHPANDE, DANISH FARUQUI
  • Publication number: 20150279805
    Abstract: Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Inventors: Omkar G. KARHADE, Nitin A. DESHPANDE, JR., Aditya Sundoctor VAIDYA, Nachiket R. RARAVIKAR, Eric J. LI
  • Publication number: 20150262968
    Abstract: The subject matter of the present description relates to methods for the precise integration of microelectronic dice within a multichip package which substantially reduce or eliminate any misalign caused by the movement of the microelectronic dice during the integration process. These methods may include the use of a temporary adhesive in conjunction with a carrier having at least one recess for microelectronic die alignment, the use of a precision molded carrier for microelectronic die alignment, the use of magnetic alignment of microelectronic dice on a reusable carrier, and/or the use of a temporary adhesive with molding processes on a reusable carrier.
    Type: Application
    Filed: June 1, 2015
    Publication date: September 17, 2015
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Ravindranath V Mahajan, Omkar Karhade, Nitin Deshpande
  • Patent number: 9123732
    Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Sandeep B. Sane, Shankar Ganapathysubramanian, Jorge Sanchez, Leonel R. Arana, Eric J. Li, Nitin A. Deshpande, Jiraporn Seangatith, Poh Chieh Benny Poon
  • Publication number: 20150237713
    Abstract: Embodiments of the present disclosure are directed towards electro-magnetic interference (EMI) shielding techniques and configurations. In one embodiment, an apparatus includes a first substrate, a die having interconnect structures coupled with the first substrate to route input/output (I/O) signals between the die and the first substrate and a second substrate coupled with the first substrate, wherein the die is disposed between the first substrate and the second substrate and at least one of the first substrate and the second substrate include traces configured to provide electro-magnetic interference (EMI) shielding for the die. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: February 19, 2014
    Publication date: August 20, 2015
    Inventors: Adel A. Elsherbini, Ravindranath Mahajan, John S. Guzek, Nitin A. Deshpande
  • Patent number: 9076882
    Abstract: The subject matter of the present description relates to methods for the precise integration of microelectronic dice within a multichip package which substantially reduce or eliminate any misalign caused by the movement of the microelectronic dice during the integration process. These methods may include the use of a temporary adhesive in conjunction with a carrier having at least one recess for microelectronic die alignment, the use of a precision molded carrier for microelectronic die alignment, the use of magnetic alignment of microelectronic dice on a reusable carrier, and/or the use of a temporary adhesive with molding processes on a reusable carrier.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: July 7, 2015
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Ravindranath V Mahajan, Omkar Karhade, Nitin Deshpande
  • Publication number: 20150187681
    Abstract: This disclosure relates generally to a system and method including a substrate and an electronic component. The substrate includes a circuit board including a hole, a routing layer, and a first interconnect portion positioned, at least in part, within the hole. The electronic component includes a second interconnect portion, coupled to the first interconnect portion, forming an interconnect between the electronic component and the routing layer.
    Type: Application
    Filed: December 26, 2013
    Publication date: July 2, 2015
    Inventors: Ravi V. Mahajan, Nitin Deshpande, John S. Guzek, Adel Elsherbini
  • Publication number: 20150179622
    Abstract: An electronic device including a solder pad structure and methods of forming an electrical interconnection are shown. Solder pads including one or more projections extending from the pads are shown where the projections occupy only a fraction of a surface area of the pads. Processes such as thermal compression bonding using solder pads as described area also shown.
    Type: Application
    Filed: December 19, 2013
    Publication date: June 25, 2015
    Inventors: Omkar Karhade, Nitin Deshpande
  • Publication number: 20150171015
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 18, 2013
    Publication date: June 18, 2015
    Inventors: Ravindranath V. Mahajan, Christopher J. Nelson, Omkar G. Karhade, Feras Eid, Nitin A. Deshpande, Shawna M. Liff
  • Publication number: 20150163904
    Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.
    Type: Application
    Filed: December 11, 2013
    Publication date: June 11, 2015
    Applicant: Intel Corporation
    Inventors: Omkar G. Karhade, John S. Guzek, Johanna M. Swan, Christopher J. Nelson, Nitin A. Deshpande, William J. Lambert, Charles A. Gealer, Feras Eid, Islam A. Salama, Kemal Aygun, Sasha N. Oster, Tyler N. Osborn
  • Publication number: 20150001717
    Abstract: Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Omkar G. Karhade, Nitin A. Deshpande, Rajendra C. Dias, Edvin Cetegen, Lars D. Skoglund
  • Publication number: 20140357020
    Abstract: The subject matter of the present description relates to methods for the precise integration of microelectronic dice within a multichip package which substantially reduce or eliminate any misalign caused by the movement of the microelectronic dice during the integration process. These methods may include the use of a temporary adhesive in conjunction with a carrier having at least one recess for microelectronic die alignment, the use of a precision molded carrier for microelectronic die alignment, the use of magnetic alignment of microelectronic dice on a reusable carrier, and/or the use of a temporary adhesive with molding processes on a reusable carrier.
    Type: Application
    Filed: June 3, 2013
    Publication date: December 4, 2014
    Inventors: Aleksandar Aleksov, Ravindranath V. Mahajan, Omkar Karhade, Nitin Deshpande